Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD データシート

32072H–AVR32–10/2012

UPRST

Read/Write

0x0041C

0x00000000

Writing a one to this bit will reset the Pipe n FIFO.

This resets the endpoint n registers (UPCFGn, UPSTAn, UPCONn) but not the endpoint configuration (ALLOC, PBK, PSIZE, 

PTOKEN, PTYPE, PEPNUM, INTFRQ).

All the endpoint mechanism (FIFO counter, reception, transmission, etc.) is reset apart from the Data Toggle management.

The endpoint configuration remains active and the endpoint is still enabled.

Writing a zero to this bit will complete the reset operation and allow to start using the FIFO.

Writing a one to this bit will enable the Pipe n.

Writing a zero to this bit will disable the Pipe n, what forces the Pipe n state to inactive and resets the pipe n registers (UPCFGn, 

UPSTAn, UPCONn) but not the pipe configuration (ALLOC, PBK, PSIZE).

31

30

29

28

27

26

25

24

-

-

-

-

-

-

-

-

23

22

21

20

19

18

17

16

PRST7

PRST6

PRST5

PRST4

PRST3

PRST2

PRST1

PRST0

15

14

13

12

11

10

9

8

-

-

-

-

-

-

-

-

7

6

5

4

3

2

1

0

PEN7

PEN6

PEN5

PEN4

PEN3

PEN2

PEN1

PEN0