Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD データシート

32072H–AVR32–10/2012

If the CPU enters a sleep mode that disables clocks used by the TC, the TC will stop functioning
and resume operation after the system wakes up from sleep mode.

The clock for the TC bus interface (CLK_TC) is generated by the Power Manager. This clock is
enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the
TC before disabling the clock, to avoid freezing the TC in an undefined state.

The TC interrupt request line is connected to the interrupt controller. Using the TC interrupt
requires the interrupt controller to be programmed first.

The Timer Counter clocks are frozen during debug operation, unless the OCD system keeps
peripherals running in debug operation.

The three channels of the Timer Counter are independent and identical in operation. The regis-
ters for channel programming are listed in 

As described in 

, each Channel has the following I/O signals.

Each channel is organized around a 16-bit counter. The value of the counter is incremented at
each positive edge of the selected clock. When the counter has reached the value 0xFFFF and
passes to 0x0000, an overflow occurs and the Counter Overflow Status bit in the Channel n Sta-
tus Register (SRn.COVFS) is set.

The current value of the counter is accessible in real time by reading the Channel n Counter
Value Register (CVn). The counter can be reset by a trigger. In this case, the counter value
passes to 0x0000 on the next valid edge of the selected clock.

Channel I/O Signals Description

Channel Signal

XC0, XC1, XC2

External Clock Inputs

TIOA

Capture mode: Timer Counter Input
Waveform mode: Timer Counter Output

TIOB

Capture mode: Timer Counter Input
Waveform mode: Timer Counter Input/Output

INT

Interrupt Signal Output

SYNC

Synchronization Input Signal