Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD データシート
製品コード
AT32UC3A3-XPLD
795
32072H–AVR32–10/2012
AT32UC3A3
29.6.5
Conversion Triggers
Conversions of the active analog channels are started with a software or a hardware trigger. The
software trigger is provided by writing a one to the START bit in the Control Register
(CR.START).
software trigger is provided by writing a one to the START bit in the Control Register
(CR.START).
The hardware trigger can be one of the TIOA outputs of the Timer Counter channels, or the
external trigger input of the ADC (TRIGGER). The hardware trigger is selected with the Trigger
Selection field in the Mode Register (MR.TRIGSEL). The selected hardware trigger is enabled
by writing a one to the Trigger Enable bit in the Mode Register (MR.TRGEN).
external trigger input of the ADC (TRIGGER). The hardware trigger is selected with the Trigger
Selection field in the Mode Register (MR.TRIGSEL). The selected hardware trigger is enabled
by writing a one to the Trigger Enable bit in the Mode Register (MR.TRGEN).
If a hardware trigger is selected, the start of a conversion is detected at each rising edge of the
selected signal. If one of the TIOA outputs is selected, the corresponding Timer Counter channel
must be programmed in Waveform Mode.
selected signal. If one of the TIOA outputs is selected, the corresponding Timer Counter channel
must be programmed in Waveform Mode.
Only one start command is necessary to initiate a conversion sequence on all the channels. The
ADC hardware logic automatically performs the conversions on the active channels, then waits
for a new request. The Channel Enable (CHER) and Channel Disable (CHDR) Registers enable
the analog channels to be enabled or disabled independently.
ADC hardware logic automatically performs the conversions on the active channels, then waits
for a new request. The Channel Enable (CHER) and Channel Disable (CHDR) Registers enable
the analog channels to be enabled or disabled independently.
If the ADC is used with a Peripheral DMA Controller, only the transfers of converted data from
enabled channels are performed and the resulting data buffers should be interpreted
accordingly.
enabled channels are performed and the resulting data buffers should be interpreted
accordingly.
Warning: Enabling hardware triggers does not disable the software trigger functionality. Thus, if
a hardware trigger is selected, the start of a conversion can be initiated either by the hardware or
the software trigger.
a hardware trigger is selected, the start of a conversion can be initiated either by the hardware or
the software trigger.
29.6.6
Sleep Mode and Conversion Sequencer
The ADC Sleep Mode maximizes power saving by automatically deactivating the ADC when it is
not being used for conversions. Sleep Mode is selected by writing a one to the Sleep Mode bit in
the Mode Register (MR.SLEEP).
not being used for conversions. Sleep Mode is selected by writing a one to the Sleep Mode bit in
the Mode Register (MR.SLEEP).
The SLEEP mode is automatically managed by a conversion sequencer, which can automati-
cally process the conversions of all channels at lowest power consumption.
cally process the conversions of all channels at lowest power consumption.
When a start conversion request occurs, the ADC is automatically activated. As the analog cell
requires a start-up time, the logic waits during this time and starts the conversion on the enabled
channels. When all conversions are complete, the ADC is deactivated until the next trigger. Trig-
gers occurring during the sequence are not taken into account.
requires a start-up time, the logic waits during this time and starts the conversion on the enabled
channels. When all conversions are complete, the ADC is deactivated until the next trigger. Trig-
gers occurring during the sequence are not taken into account.
The conversion sequencer allows automatic processing with minimum processor intervention
and optimized power consumption. Conversion sequences can be performed periodically using
a Timer/Counter output. The periodic acquisition of several samples can be processed automat-
ically without any intervention of the processor thanks to the Peripheral DMA Controller.
and optimized power consumption. Conversion sequences can be performed periodically using
a Timer/Counter output. The periodic acquisition of several samples can be processed automat-
ically without any intervention of the processor thanks to the Peripheral DMA Controller.
Note:
The reference voltage pins always remain connected in normal mode as in sleep mode.