Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD データシート
製品コード
AT32UC3A3-XPLD
801
32072H–AVR32–10/2012
AT32UC3A3
29.7.4
Channel Disable Register
Name:
CHDR
Access Type:
Write-only
Offset:
0x14
Reset Value:
0x00000000
• CHn: Channel n Disable
Writing a one to these bits will clear the corresponding bit in CHSR.
Writing a zero to these bits has no effect.
These bits always read a zero.
Warning: If the corresponding channel is disabled during a conversion or if it is disabled then reenabled during a conversion, its
associated data and
its
corresponding EOC and OVRE flags in SR are unpredictable.
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
–
–
–
–
–
–
–
–
7
6
5
4
3
2
1
0
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0