Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD データシート
製品コード
AT32UC3A3-XPLD
814
32072H–AVR32–10/2012
AT32UC3A3
30.6.1
Control Register
Name:
CONTROL
Access Type:
Read/Write
Offset:
0x00
Reset Value:
0x00000000
• CHnRES: Channel Counter Reset
Writting a one to this bit will reset the counter in the channel n.
Writting a zero to this bit has no effect.
This bit always reads as zero.
• CHnOF: Channel Overflow Freeze
1: All channel n registers are frozen just before DATA or STALL overflows.
0: The channel n registers are reset if DATA or STALL overflows.
• CHnEN: Channel Enabled
1: The channel n is enabled.
0: The channel n is disabled.
31
30
29
28
27
26
25
24
-
-
-
-
-
-
-
-
23
22
21
20
19
18
17
16
-
-
-
-
CH3RES
CH2RES
CH1RES
CH0RES
15
14
13
12
11
10
9
8
-
-
-
-
CH3OF
CH2OF
CH1OF
CH0OF
7
6
5
4
3
2
1
0
-
-
-
-
CH3EN
CH2EN
CH1EN
CH0EN