Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD データシート
製品コード
AT32UC3A3-XPLD
84
32072H–AVR32–10/2012
AT32UC3A3
8.6.1
Control Register
Name: CTRL
Access Type:
Read/Write
Offset:
0x00
Reset Value:
0x00010000
• CLKEN: Clock Enable
1: The clock is enabled.
0: The clock is disabled.
• PSEL: Prescale Select
Selects prescaler bit PSEL as source clock for the RTC.
• BUSY: RTC Busy
This bit is set when the RTC is busy and will discard writes to TOP, VAL, and CTRL.
This bit is cleared when the RTC accepts writes to TOP, VAL, and CTRL.
• CLK32: 32 KHz Oscillator Select
1: The RTC uses the 32 KHz oscillator as clock source.
0: The RTC uses the RC oscillator as clock source.
• WAKEN: Wakeup Enable
1: The RTC wakes up the CPU from sleep modes.
0: The RTC does not wake up the CPU from sleep modes.
• PCLR: Prescaler Clear
Writing a one to this bit clears the prescaler.
Writing a zero to this bit has no effect.
This bit always reads as zero.
• EN: Enable
1: The RTC is enabled.
0: The RTC is disabled.
31
30
29
28
27
26
25
24
-
-
-
-
-
-
-
-
23
22
21
20
19
18
17
16
-
-
-
-
-
-
-
CLKEN
15
14
13
12
11
10
9
8
-
-
-
-
PSEL
7
6
5
4
3
2
1
0
-
-
-
BUSY
CLK32
WAKEN
PCLR
EN