Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD データシート
製品コード
AT32UC3A3-XPLD
870
32072H–AVR32–10/2012
AT32UC3A3
32. Memory Stick Interface (MSI)
Rev: 2.1.0.0
32.1
Features
•
Memory Stick ver. 1.x & Memory Stick PRO support
•
Memory Stick serial clock (serial mode: 20 MHz max., parallel mode: 40 MHz max.)
•
Data transmit/receive FIFO of 64 bits x 4
•
16 bits CRC circuit
•
DMACA transfer support
•
Card insertion/removal detection
32.2
Overview
The Memory Stick Interface (MSI) is a host controller that supports Memory Stick Version 1.X
and Memory Stick PRO.
and Memory Stick PRO.
The communication protocol with the Memory Stick is started by write from the CPU to the com-
mand register. When the protocol finishes, the CPU is notified that the protocol has ended by an
interrupt request. When the protocol is started and enters the data transfer state, data is
requested by issuing a DMA transfer request (via DMACA) or an interrupt request to the CPU.
mand register. When the protocol finishes, the CPU is notified that the protocol has ended by an
interrupt request. When the protocol is started and enters the data transfer state, data is
requested by issuing a DMA transfer request (via DMACA) or an interrupt request to the CPU.
The RDY time out time when the handshake state (BS2 in read protocol, BS3 for write protocol)
is established in communication with the Memory Stick can be designated as the number of
Memory Stick transfer clocks. When a time out occurs, the CPU is notified that the protocol has
ended due to a time out error by an interrupt request.
is established in communication with the Memory Stick can be designated as the number of
Memory Stick transfer clocks. When a time out occurs, the CPU is notified that the protocol has
ended due to a time out error by an interrupt request.
CRC circuit can be set off for test mode purpose. When CRC is off, CRC is not added to the data
transmitted to the Memory Stick.
transmitted to the Memory Stick.
An interrupt request can also be issued to the CPU when a Memory Stick is inserted or removed.
Figure 32-1. Read packet
RDY/BSY
CRC
DATA
TPC
INT
INT
BS0
BS1
BS2
BS3
BS0
BS
SDIO / DATA[3:0]
SCLK
Memory Stick
Host
Memory Stick