Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD データシート

32072H–AVR32–10/2012

The WDT is enabled by writing a one to the Enable bit in the Control register (CTRL.EN). This
also enables the system RC clock (CLK_RCSYS) for the prescaler. The Prescale Select field
(PSEL) in the CTRL register selects the watchdog time-out period:

T

WDT

 = 2

(PSEL+1)

 / f

RC

The next time-out period will begin as soon as the watchdog reset has occurred and count down
during the reset sequence. Care must be taken when selecting the PSEL field value so that the
time-out period is greater than the startup time of the chip, otherwise a watchdog reset can reset
the chip before any code has been run.

To avoid accidental disabling of the watchdog, the CTRL register must be written twice, first with
the KEY field set to 0x55, then 0xAA without changing the other bits. Failure to do so will cause
the write operation to be ignored, and the CTRL register value will not change.

The Clear register (CLR) must be written with any value with regular intervals shorter than the
watchdog time-out period. Otherwise, the device will receive a soft reset, and the code will start
executing from the boot vector.

When the WDT is enabled, it is not possible to enter Static mode. Attempting to do so will result
in entering Shutdown mode, leaving the WDT operational.

WDT Register Memory Map

0x00

Control Register

CTRL

Read/Write

0x00000000

0x04

Clear Register

CLR

Write-only

0x00000000