Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD データシート

32072H–AVR32–10/2012

9.

Return to Run-Test/Idle.

This instruction selects the 1-bit Bypass Register as Data Register.

Starting in Run-Test/Idle, the CLAMP instruction is accessed the following way:

1.

Select the IR Scan path.

2.

In Capture-IR: The IR output value is latched into the shift register.

3.

In Shift-IR: The instruction register is shifted by the TCK input.

4.

Return to Run-Test/Idle.

5.

Select the DR Scan path.

6.

In Capture-DR: A logic ‘0’ is loaded into the Bypass Register.

7.

In Shift-DR: Data is scanned from TDI to TDO through the Bypass register.

8.

Return to Run-Test/Idle.

The 32-bit AVR defines a number of private JTAG instructions, not defined by the JTAG stan-
dard. Each instruction is briefly described in text, with details following in table form.

This instruction allows Nexus-compliant access to the On-Chip Debug registers through the
SAB. The 7-bit register index, a read/write control bit, and the 32-bit data is accessed through
the JTAG port.

The data register is alternately interpreted by the SAB as an address register and a data regis-
ter. The SAB starts in address mode after the NEXUS_ACCESS instruction is selected, and
toggles between address and data mode each time a data scan completes with the busy bit
cleared.

NOTE: The polarity of the direction bit is inverse of the Nexus standard.

Table 35-14. CLAMP Details

IR input value

00110 (0x06)

IR output value

p0001

DR Size

1

DR input value

x

DR output value

x

Table 35-15. BYPASS Details

IR input value

11111 (0x1F)

IR output value

p0001

DR Size

1

DR input value

x

DR output value

x