Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD データシート

32072H–AVR32–10/2012

Table 36-22. Channel Conversion Time and ADC Clock

ADC Clock Frequency

10-bit resolution mode

5

MHz

8-bit resolution mode

8

MHz

Startup Time

Return from Idle Mode

20

µs

Track and Hold Acquisition Time

600

ns

Conversion Time

ADC Clock = 5 MHz

2

µs

ADC Clock = 8 MHz

1.25

µs

Throughput Rate

ADC Clock = 5 MHz

384

 (1)

1. Corresponds to 13 clock cycles: 3 clock cycles for track and hold acquisition time and 10 clock cycles for conversion.

kSPS

ADC Clock = 8 MHz

533

 (2)

2. Corresponds to 15 clock cycles: 5 clock cycles for track and hold acquisition time and 10 clock cycles for conversion.

kSPS

Table 36-23. ADC Power Consumption

Current Consumption on VDDANA

 (1)

1. Including internal reference input current

On 13 samples with ADC clock = 5 MHz

1.25

mA

Table 36-24. Analog Inputs

Input Voltage Range

0

VDDANA

V

Input Leakage Current

1

µA

Input Capacitance

7

pF

Input Resistance

350

850

Ohm

Table 36-25. Transfer Characteristics in 8-bit mode

Resolution

8

Bit

Absolute Accuracy

ADC Clock = 5 MHz

0.8

LSB

ADC Clock = 8 MHz

1.5

LSB

Integral Non-linearity

ADC Clock = 5 MHz

0.35

0.5

LSB

ADC Clock = 8 MHz

0.5

1.5

LSB

Differential Non-linearity

ADC Clock = 5 MHz

0.3

0.5

LSB

ADC Clock = 8 MHz

0.5

1.5

LSB

Offset Error

ADC Clock = 5 MHz

-1.5

1.5

LSB

Gain Error

ADC Clock = 5 MHz

-0.5

0.5

LSB