Atmel SAM4L Xplained Pro Evaluation Kit Atmel ATSAM4L-XPRO ATSAM4L-XPRO データシート
製品コード
ATSAM4L-XPRO
1050
42023E–SAM–07/2013
ATSAM4L8/L4/L2
• DMASK[7:0], each bit is a mask for DATA field. When DMASK[x]=1, DATA[x] is not written to
display memory,
).
To update more than 8 segments, PDCA must transfer multiple words before shadow memory is
updated. This number of words must also be written in SIZE field in Automated Bit Mapping
Configuration register (ABMCFG), it indicates the number of writes in display memory to form a
frame.
updated. This number of words must also be written in SIZE field in Automated Bit Mapping
Configuration register (ABMCFG), it indicates the number of writes in display memory to form a
frame.
To make an automated animation of N states with M segments, PDCA must be configured to
transfer N x SIZE (= M/8 or more) words. Note that if segments are at any position in display
memory, DMASK is used then PDCA size can be up to N x M.
transfer N x SIZE (= M/8 or more) words. Note that if segments are at any position in display
memory, DMASK is used then PDCA size can be up to N x M.
The display period (animation update) is defined by writing the number of frame in TIM.FCx. The
frame counter is selected by writing its number in ABMCFG.FCS.
frame counter is selected by writing its number in ABMCFG.FCS.
Animation can be repeated if PDCA is configured to repeat the whole transfer.
39.6.13
Contrast Adjustment
Contrast is defined by the maximum value of V
LCD
. The higher value the higher contrast.
Fine Contrast value (FCST) in CFG register is a signed value (two’s complement) which defines
the maximum voltage V
the maximum voltage V
LCD
on segment and common terminals. New value takes effect at the
beginning of next frame.
39.6.14
Interrupts
LCDCA can generate an interrupt at the beginning of a frame. When Frame Counter 0 Rollover
bit (SR.FC0R) is set to one and interrupt is not masked, LCDCA interrupt is pending.
bit (SR.FC0R) is set to one and interrupt is not masked, LCDCA interrupt is pending.
Moreover Frame Counter 0 (TIM.FC0) can be used to select the interrupt period generation.
This mode can provide a useful time base to update LCD.
If TIM.FC0PB=0:
This mode can provide a useful time base to update LCD.
If TIM.FC0PB=0:
If TIM.FC0PB=1:
Note that in low power waveform mode, frame period is twice the frame period in standard wave-
form mode.
form mode.
An interrupt request will be generated if the corresponding bit in the Interrupt Mask Register
(IMR) is set. Bits in IMR are set by writing a one to the corresponding bit in the Interrupt Enable
Register (IER) and cleared by writing a one to the corresponding bit in the Interrupt Disable Reg-
ister (IDR). The interrupt request remains active until the corresponding bit in SR is cleared by
writing a one to the corresponding bit in Status Clear Register (SCR).
(IMR) is set. Bits in IMR are set by writing a one to the corresponding bit in the Interrupt Enable
Register (IER) and cleared by writing a one to the corresponding bit in the Interrupt Disable Reg-
ister (IDR). The interrupt request remains active until the corresponding bit in SR is cleared by
writing a one to the corresponding bit in Status Clear Register (SCR).
39.6.15
LCD Wake Up
LCD controller can wake up CPU with the interrupt request line. But in sleep modes where APB
clocks are off, LCD wake up mechanism must be enabled to wake up CPU.
clocks are off, LCD wake up mechanism must be enabled to wake up CPU.
V
LCD
3V
FCST
(
+
0 016V
,
)
×
=
Interrupt Period
TIM.FC0
8
×
(
) 1
+
(
) Frame Period
×
=
Interrupt Period
TIM.FC0
1
+
(
) Frame Period
×
=