Taskit ARM9 CPU-module with Linux Stamp9261-series Stamp9261 (64F/64R) 542310 データシート
製品コード
542310
4.18. Peripheral DMA Controller (PDC)
The PDC provides both a receive and a transmit channel for each of the following full-duplex devices:
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USARTs
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Debug UART
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SPIs
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SSCs
The following half duplex device uses one bidirectional DMA channel:
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MCI
The DMA controllers of the USB Host interface and the LCD controller have specific characteristics
and are not part of the PDC.
and are not part of the PDC.
The address space of the DMA registers of one DMA channel as well as the interrupt of that channel
are assigned to the appropriate peripheral. The PDC registers thus do not occupy a contiguous
address range.
are assigned to the appropriate peripheral. The PDC registers thus do not occupy a contiguous
address range.
a) PDC Registers
A DMA channel consists of a
A DMA channel consists of a
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pointer register
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counter register
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new pointer register
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new counter register
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status register (enable/disable status)
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control (enable/disable) register
The counter register has 16 bits. The maximum buffer size for a single DMA transfer is thus limited to
64kB. The PDC supports 8-bit, 16-bit and 32-bit data words. They are selected according to the
requirements of the associated peripheral device.
64kB. The PDC supports 8-bit, 16-bit and 32-bit data words. They are selected according to the
requirements of the associated peripheral device.
b) PDC Interrupts
There are four kinds of interrupt generated by the PDC:
There are four kinds of interrupt generated by the PDC:
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End of Receive Buffer
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End of Transmit Buffer
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Receive Buffer Full
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Transmit Buffer Empty
The "End of Receive Buffer" / "End of Transmit Buffer" interrupts signify that the DMA counter has
reached zero. The DMA pointer and counter register will be reloaded from the reload registers ("DMA
new pointer register" and "DMA new counter register") provided that the "DMA new counter register"
has a non-zero value. Otherwise a "Receive Buffer Full" or, respectively, a "Transmit Buffer Empty"
interrupt is generated, and the DMA transfer terminates. Both reload registers are set to zero
automatically after having been copied to the DMA pointer and counter registers.
reached zero. The DMA pointer and counter register will be reloaded from the reload registers ("DMA
new pointer register" and "DMA new counter register") provided that the "DMA new counter register"
has a non-zero value. Otherwise a "Receive Buffer Full" or, respectively, a "Transmit Buffer Empty"
interrupt is generated, and the DMA transfer terminates. Both reload registers are set to zero
automatically after having been copied to the DMA pointer and counter registers.
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