STMicroelectronics EVALHVLED815W10 and EVALHVLED815W15 Evaluation Board for the Offline LED Driver with Primary-Sensing and High Power Fact EVALHVLED815W10 データシート
製品コード
EVALHVLED815W10
DocID023409 Rev 5
29/34
HVLED815PF
Device description
34
Finally the current sense resistor R
SENSE
can be estimated in order to select the
desiderated average output current value:
Equation 24
where V
CLED
is internally defined (0.2 V typical - see
).
System design tips
Starting from the previous estimated components value, further fine-tuning on the real LED
driver board could be necessary and it can be easily done considering that:
driver board could be necessary and it can be easily done considering that:
–
Decreasing/increasing the R
PF
resistor value, the power factor effect
increases/decreases.
–
Decreasing/increasing the R
OS
resistor value, the line regulation effect
increases/decreases.
–
Decreasing/increasing the R
OS
resistor value, the R
A
+ R
B
resistors value should
be increased/decreased to keep the desiderated voltage across the C
OS
capacitor
).
–
Decreasing/increasing the R
SENSE
resistor value the average output current
increases/decreases (
4.12 Layout
recommendations
A proper printed circuit board layout is essential for correct operation of any switch-mode
converter and this is true for the HVLED815PF device as well. Careful component placing,
correct traces routing, appropriate traces widths and compliance with isolation distances are
the major issues.
converter and this is true for the HVLED815PF device as well. Careful component placing,
correct traces routing, appropriate traces widths and compliance with isolation distances are
the major issues.
In particular:
Current sense resistor (R
SENSE
) should be connected as close as possible to the
SOURCE pin, maintaining the trace for the GND as short as possible.
Resistor connected on CS pin (R
OS
, R
PF
, R
1
) should be connected as close as
possible to the pin.
Compensation network (R
COMP
, C
COMP
) should be connected as close as possible to
the COMP pin, maintaining the trace for the GND as short as possible.
Signal ground should be routed separately from power ground, as well from the sense
resistor trace.
resistor trace.
DMG partition resistors (R
DMG
, R
FB
) should be connected as close as possible to the
DMG pin, minimizing the equivalent parasitic capacitor on DMG pin.