Aeneon 2048MB DDR2 667MHz Fully Buffered AET861FB00-30D データシート
製品コード
AET861FB00-30D
AENEON™ Data Sheet
2
Revision 1.10, 2008-05
A Qimonda AG Brand
Doc. # 12272007-OKYD-PLKJ
DDR2 Fully Buffered
Memory Module
TABLE 2
Speed Grade Definition
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a
differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS,
RDQS / RDQS, input reference level is the crosspoint when in differential strobe mode.
3) Inputs are not recognized as valid until
V
REF
stabilizes. During the period before
V
REF
stabilizes, CKE = 0.2 x
V
DDQ
4) The output timing reference voltage level is
V
TT
.
5) t
RAS.MAX
is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is
equal to 9 x
t
REFI
.
6) Products released after 2007-08-01 can support
t
RAS.MIN
= 40 ns for all DDR2 speed sort.
7) For products released after 2007-08-01.
Speed Grade
PC2
–6400
–5300
CAS-RCD-RP latencies
5–5–5
5–5–5
Parameter
Symbol
Min.
Max.
Min.
Max.
Unit
Note
Clock Period
@ CL = 3
t
CK
5
8
5
8
ns
@ CL = 4
t
CK
3.75
8
3.75
8
ns
@ CL = 5
t
CK
2.5
8
3
8
ns
@ CL = 6
t
CK
2.5
8
—
—
ns
@ CL = 7
t
CK
2.5
8
—
—
ns
Row Active Time
t
RAS
45
70k
45
70k
ns
Row Active Time
t
RAS
40
70k
40
70k
ns
Row Cycle Time
t
RC
57.5
—
60
—
ns
Row Cycle Time
t
RC
52.5
—
55
–
ns
RAS-CAS-Delay
t
RCD
12.5
—
15
—
ns
Row Precharge Time
t
RP
12.5
—
15
—
ns