Aeneon 2048MB DDR2 667MHz Fully Buffered AET861FB00-30D データシート
製品コード
AET861FB00-30D
AENEON™ Data Sheet
4
Revision 1.10, 2008-05
A Qimonda AG Brand
Doc. # 12272007-OKYD-PLKJ
DDR2 Fully Buffered
Memory Module
Attention:Stresses greater than those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
TABLE 5
FB-DIMM Latency Range
Voltage on
V
DDQ
pin relative to
V
SS
V
DDQ
–0.5
+2.3
V
Voltage on
V
DDL
pin relative to
V
SS
V
DDL
–0.5
+2.3
V
Voltage on any pin relative to
V
SS
V
IN
,
V
OUT
–0.3
+1.75
V
Voltage on
V
TT
pin relative to
V
SS
V
TT
–0.5
+2.3
V
–
Storage Temperature
T
STG
–55
+100
°C
2)3)
1) Stresses greater than those listed under “Absolute Maximum Ratings“ may cause permanent damage to the device. This
is a stress rating only and functional operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2) When
V
DD
and
V
DDQ
and
V
DDL
are less than 500 mV;
V
REF
may be equal to or less than 300 mV.
3) Storage Temperature is the case surface temperature on the center/top side of the DRAM.
Parameter
DDR2–800D
DDR2–667D
Unit
Note
Min.
Nom.
Max.
Min.
Typ.
Max.
t
C2D_DIMM
Tbd
19.35
Tbd
17.5
21
21.5
ns
1)2)
1) For DDR-800D and DDR-800E no industry standard values are avalible for Min. and Max parameter.
2) Measured delay at FB-DIMM gold finger between the center of the1st UI of command frame on the primary southbound
2) Measured delay at FB-DIMM gold finger between the center of the1st UI of command frame on the primary southbound
lane 81 (connector pins 102 & 103) and the center of the 1st UI of return data on the primary northbound lane 0
(connector pins 22 & 23) – [CL (DRAM CAS latency) value] * [frame clock period – AL (DRAM additional latency) value
* frame clock period].
(connector pins 22 & 23) – [CL (DRAM CAS latency) value] * [frame clock period – AL (DRAM additional latency) value
* frame clock period].
t
RESAMPLE_DIMM_SB
Tbd
1.68
Tbd
1.4
1.69
2.4
ns
2)3)
3) Measured delay at FB-DIMM gold finger between the center of the 1st UI of a frame on the primary southbound lane 8
(connector pins 102 & 103) and the center of the 1st UI of the same frame on the secondary southbound lane 8
(connector pins 222 & 223).
(connector pins 222 & 223).
t
RESAMPLE_DIMM_NB
Tbd
1.48
Tbd
1.3
1.73
2.3
ns
2)4)
4) Measured delay at FB-DIMM gold finger between the center of the 1st UI of a frame on the secondary northbound lane
0 (connector pins 142 & 143) and the center of the 1st UI of the same frame on the primary northbound lane 0 (connector
pins 22 & 23).
pins 22 & 23).
t
RESYNC_DIMM_SB
Tbd
2.66
Tbd
2.5
2.8
3.7
ns
2)5)
t
RESYNC_DIMM_NB
Tbd
2.54
Tbd
2.4
2.8
3.6
ns
2)6)
Parameter
Symbol
Rating
Unit
Notes
Min.
Max.