Aeneon 4096MB DDR2 667MHz Registered AET961PD00-30D データシート

AENEON™ Data Sheet

2

Revision 1.10, 2008-05

A Qimonda AG Brand

Doc. # 01282008-5Q5R-K6FR

DDR2 Register

Memory Module

1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a 

differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.

2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, 

RDQS / RDQS, input reference level is the crosspoint when in differential strobe mode.

3) Inputs are not recognized as valid until 

REF

 stabilizes. During the period before 

REF

 stabilizes, CKE = 0.2 x 

DDQ

4) The output timing reference voltage level is 

TT

. 

5)

RAS.MAX 

is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is 

equal to 9 x 

REFI

.

6) Products released after 2007-08-01 can support 

RAS.MIN

 = 40 ns for all DDR2 speed sort.

7) For products released after 2007-08-01.

Row Active Time 

RAS

45

70k

ns

Row Active Time 

RAS

40

70k

ns

Row Cycle Time

RC

60

—

ns

Row Cycle Time

RC

55

–

ns

RAS-CAS-Delay

RCD

15

—

ns

Row Precharge Time

RP

15

—

ns

Device Supply Voltage

DD

1.7

1.8

1.9

V

Output Supply Voltage

DDQ

1.7

1.8

1.9

V

1)

1) Under all conditions, 

DDQ

 must be less than or equal to 

DD

Input Reference Voltage

REF

0.49 × 

DDQ

0.5 × 

DDQ

0.51 × 

DDQ

V

2)

2) Peak to peak AC noise on 

REF

 may not exceed ± 2% 

REF

(DC).

REF

 is also expected to track noise in 

DDQ

.

SPD Supply Voltage

DDSPD

1.7

—

3.6

V

DC Input Logic High

IH(DC)

REF

+ 0.125 —

DDQ

+ 0.3

V

DC Input Logic Low

IL (DC

)

–  0.30

—

REF

– 0.125

V

In / Output Leakage Current

L

– 5

—

5

μA

3)

3) Input voltage for any connector pin under test of 0 V ≤ 

IN

 ≤ 

DDQ

 + 0.3 V; all other pins at 0 V. Current is per pin