Bourns Surge arrester SMT 170 V 90 A 1 pc(s) TISP6NTP2CDR-S データシート

MARCH 2002 – REVISED JULY 2008

Specifications are subject to change without notice.

Customers should verify actual device performance in their specific applications.

°

≤

≤

°

The systems described often have the need to source two POTS (Plain Old Telephone Service) lines, one for a telephone and the other for a
facsimile machine. In a single surface mount package, the TISP6NTP2C protects the two POTS line SLICs (Subscriber Line Interface Circuits)
against overvoltages caused by lightning, a.c. power contact and induction.

The TISP6NTP2C has an array of four buffered P-gate forward conducting thyristors with twin commoned gates and a common anode
connection. Each thyristor cathode has a separate terminal connection. An antiparallel anode-cathode diode is connected across each
thyristor. The buffer transistors reduce the gate supply current.

In use, the cathodes of an TISP6NTP2C thyristors are connected to the four conductors of two POTS lines (see applications information).
Each gate is connected to the appropriate negative voltage battery feed of the SLIC driving that line pair. By having separate gates, each SLIC
can be protected at a voltage level related to the negative supply voltage of that individual SLIC. The anode of the TISP6NTP2C is connected
to the SLIC common. The TISP6NTP2C voltage and current ratings also make it suitable for the protection of ISDN d.c. feeds of down to
-115 V (ETSI Technical Report ETR 080:1993, ranges 1 to 5).

Positive overvoltages are clipped to common by forward conduction of the TISP6NTP2C antiparallel diode. Negative overvoltages are initially
clipped close to the SLIC negative supply by emitter follower action of the TISP6NTP2C buffer transistor. If sufficient clipping current flows,
the TISP6NTP2C thyristor will regenerate and switch into a low voltage on-state condition. As the overvoltage subsides, the high holding
current of the TISP6NTP2C 

helps prevent d.c. latchup.

C

G

Gate decoupling capacitor

100

220

nF

R

S

Series resistor for GR-1089-CORE intra-building surge survival,  section 4.5.9, tests 1 and 2

5

50

Ω

Series resistor for K.20, K.21 and K.45 coordination with a 400 V primary protector

10

50

Ω

Repetitive peak off-state voltage, V

GK

= 0

V

DRM

-170

V

Repetitive peak gate-cathode voltage, V

KA

= 0

V

GKRM

-167

V

Non-repetitive peak on-state pulse current (see Notes 1 and 2)

I

PPSM

A

10/1000 (Telcordia (Bellcore) GR-1089-CORE, Issue 2, February 1999, Section 4)

5/320 (ITU-T K.20, K.21& K.45, K.44 open-circuit voltage wave shape 10/700)

2/10 (Telcordia (Bellcore) GR-1089-CORE, Issue 2, February 1999, Section 4)

25

40

90

Non-repetitive peak on-state current, 50 Hz/60 Hz (see Notes 1 and 2)

I

TSM

A

0.1 s

7

1 s

5 s

300 s

900 s

2.7

1.5

0.45

0.43

Non-repetitive peak gate current, 1/2

µ

s pulse, cathodes commoned (see Note 1)

I

GSM

+25

A

Operating free-air temperature range

T

A

-40 to +85

°

C

Junction temperature

T

J

-40 to +150

°

C

Storage temperature range

T

stg

-40 to +150

°

C

NOTES: 1. Initially, the protector must be in thermal equilibrium. The surge may be repeated after the device returns to its initial conditions.

Gate voltage range is -20 V to -155 V. 

2. These non-repetitive rated currents are peak values for either polarity. The rated current values may be applied to any cathode-

anode terminal pair. Additionally, all cathode-anode terminal pairs may have their rated current values applied simultaneously (in
this case the anode terminal current will be four times the rated current value of an individual terminal pair).