Analog Devices AD9763 Evaluation Board AD9763-EBZ AD9763-EBZ データシート

 

Rev. G | Page 29 of 44 

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74

Figure 75 shows the AD9763/AD9765/AD9767 configured to 
provide a unipolar output range of approximately 0 V to 0.5 V 
for a doubly terminated 50 Ω cable, because the nominal full-
scale current (I

OUTFS

) of 20 mA flows through the equivalent 

R

LOAD

 of 25 Ω. In this case, R

LOAD

 represents the equivalent load 

resistance seen by I

OUTA

 or I

OUTB

. The unused output (I

OUTA

 or I

OUTB

) 

can be connected directly to ACOM or via a matching R

LOAD

. 

Different values of I

OUTFS

 and R

LOAD

 can be selected as long as the 

positive compliance range is adhered to. One additional 
consideration in this mode is the INL (see the Analog Outputs 
section). For optimum INL performance, the single-ended, 
buffered voltage output configuration is suggested. 

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75

Figure 76 shows a buffered single-ended output configuration 
in which the U1 op amp performs an I-V conversion on the 
AD9763/AD9765/AD9767 output current. U1 maintains I

OUTA

 

(or I

OUTB

) at a virtual ground, thus minimizing the nonlinear 

output impedance effect on the INL performance of the DAC, 
as described in the Analog Outputs section. Although this single-
ended configuration typically provides the best dc linearity 
performance, its ac distortion performance at higher DAC update 
rates may be limited by the slewing capabilities of U1. U1 
provides a negative unipolar output voltage, and its full-scale 
output voltage is simply the product of R

FB

 and I

OUTFS

. Set the 

full-scale output within U1’s voltage output swing capabilities 
by scaling I

OUTFS

 and/or R

FB

. An improvement in ac distortion 

performance may result with a reduced I

OUTFS

 because the signal 

current U1 has to sink will be subsequently reduced. 

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76

Many applications seek high speed and high performance under 
less than ideal operating conditions. In these applications, the 
implementation and construction of the printed circuit board is 
as important as the circuit design. Proper RF techniques must 
be used for device selection, placement, and routing as well as 
power supply bypassing and grounding to ensure optimum 
performance. Figure 92 to Figure 93 illustrate recommended 
printed circuit board ground, power, and signal plane layouts 
that are implemented on the AD9763/AD9765/AD9767 
evaluation board. 

One factor that can measurably affect system performance is 
the ability of the DAC output to reject dc variations or ac noise 
superimposed on the analog or digital dc power distribution. 
This is referred to as the power supply rejection ratio (PSRR). 
For dc variations of the power supply, the resulting performance 
of the DAC directly corresponds to a gain error associated with 
the DAC’s full-scale current, I

OUTFS

. AC noise on the dc supplies 

is common in applications where the power distribution is 
generated by a switching power supply. Typically, switching 
power supply noise occurs over the spectrum of tens of 
kilohertz to several megahertz. The PSRR vs. frequency of the 
AD9763/AD9765/AD9767 AVDD supply over this frequency 
range is shown in Figure 77. 

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77