Intel 1.40 GHz RH80532NC017256 データシート
製品コード
RH80532NC017256
Mobile Intel
®
Celeron
®
Processor (0.13 µ)
Micro-FCBGA and Micro-FCPGA Packages Datasheet
298517-006 Datasheet
25
3.2.4.3 Noise
The signal quality of the VTTPWRGD signal is critical to the correct operation of the processor. Every
effort should be made to ensure this signal is monotonic in the transition region. If noise or glitches are
present on this signal, it must be kept to less than 100 mV of a voltage drop from the highest voltage
level received to that point. This glitch must remain less than 100 mV until the excursion ends by the
voltage returning to the highest voltage previously received. Please see Figure 4 for an example graph of
this situation and requirements.
effort should be made to ensure this signal is monotonic in the transition region. If noise or glitches are
present on this signal, it must be kept to less than 100 mV of a voltage drop from the highest voltage
level received to that point. This glitch must remain less than 100 mV until the excursion ends by the
voltage returning to the highest voltage previously received. Please see Figure 4 for an example graph of
this situation and requirements.
Figure 4. Noise Estimation
3.3
System Bus Clock and Processor Clocking
The BCLK and BCLK# clock inputs directly control the operating speed of the system bus interface. All
system bus timing parameters are specified with respect to the crossing point of the rising edge of the
BCLK input and falling edge of the BCLK# input. The Mobile Intel Celeron Processor core frequency is
a multiple of the BCLK frequency. The processor core frequency is configured during manufacturing.
The configured bus ratio is visible to software in the Power-on configuration register. See Section 7.2 for
details.
system bus timing parameters are specified with respect to the crossing point of the rising edge of the
BCLK input and falling edge of the BCLK# input. The Mobile Intel Celeron Processor core frequency is
a multiple of the BCLK frequency. The processor core frequency is configured during manufacturing.
The configured bus ratio is visible to software in the Power-on configuration register. See Section 7.2 for
details.
Multiplying the bus clock frequency is necessary to increase performance while allowing for easier
distribution of signals within the system. Clock multiplication within the processor is provided by the
internal Phase Lock Loop (PLL), which requires constant frequency BCLK and BCLK# inputs. During
Reset or on exit from the Deep Sleep state, the PLL requires some amount of time to acquire the phase
of BCLK and BCLK#. This time is called the PLL lock latency, which is specified in Section 3.6, AC
timing parameters T18 and T47.
distribution of signals within the system. Clock multiplication within the processor is provided by the
internal Phase Lock Loop (PLL), which requires constant frequency BCLK and BCLK# inputs. During
Reset or on exit from the Deep Sleep state, the PLL requires some amount of time to acquire the phase
of BCLK and BCLK#. This time is called the PLL lock latency, which is specified in Section 3.6, AC
timing parameters T18 and T47.