Intel 1.40 GHz RH80532NC017256 データシート
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製品コード
RH80532NC017256
Mobile Intel
®
Celeron
®
Processor (0.13 µ)
Micro-FCBGA and Micro-FCPGA Packages Datasheet
298517-006 Datasheet
57
Figure 21. Quick Start/Deep Sleep Timing (DPSLP# Assertion Method)
T
w
stpgnt
BCLK
STPCLK#
CPU bus
DPSLP#
Compatibility
Signals
Changing
Normal
Quick Start
Deep Sleep
Quick Start
Normal
Frozen
T
v
T
y
T
z
T
x
V00103-00
NOTES:
T
v
=T45 (Stop Grant Acknowledge Bus Cycle Completion to DPSLP# assertion)
T
w
= T46 (Setup Time to Input Signal Hold Requirement)
T
x
=T47 (Deep Sleep PLL Lock Latency)
T
y
=T48 (PLL lock to STPCLK# Hold Time)
T
z
=T49 (Input Signal Hold Time)