Intel ULV 383 LE80536VC0011M データシート
製品コード
LE80536VC0011M
Mobile Intel
®
Celeron
®
Processor (0.18µ) in BGA2 and Micro-PGA2 Packages
283654-003 Datasheet
15
The processor will return to the Stop Grant state after the completion of a BINIT# bus
initialization unless STPCLK# has been deasserted. RESET# assertion will cause the processor to
immediately initialize itself, but the processor will stay in the Stop Grant state after initialization
until STPCLK# is deasserted. A transition to the Sleep state can be made by the assertion of the
SLP# signal.
initialization unless STPCLK# has been deasserted. RESET# assertion will cause the processor to
immediately initialize itself, but the processor will stay in the Stop Grant state after initialization
until STPCLK# is deasserted. A transition to the Sleep state can be made by the assertion of the
SLP# signal.
While in the Stop Grant state, assertions of FLUSH#, SMI#, INIT#, INTR, and NMI (or
LINT[1:0]) will be latched by the processor. These latched events will not be serviced until the
processor returns to the Normal state. Only one of each event will be recognized upon return to the
Normal state.
LINT[1:0]) will be latched by the processor. These latched events will not be serviced until the
processor returns to the Normal state. Only one of each event will be recognized upon return to the
Normal state.
2.2.5 Quick
Start
State
This is a mode entered by the processor with the assertion of the STPCLK# signal when it is
configured for the Quick Start state (via the A15# strapping option). In the Quick Start state the
processor is only capable of acting on snoop transactions generated by the system bus priority
device. Because of its snooping behavior, Quick Start can only be used in a uniprocessor (UP)
configuration.
configured for the Quick Start state (via the A15# strapping option). In the Quick Start state the
processor is only capable of acting on snoop transactions generated by the system bus priority
device. Because of its snooping behavior, Quick Start can only be used in a uniprocessor (UP)
configuration.
A transition to the Deep Sleep state can be made by stopping the clock input to the processor. A
transition back to the Normal state (from the Quick Start state) is made only if the STPCLK#
signal is deasserted.
transition back to the Normal state (from the Quick Start state) is made only if the STPCLK#
signal is deasserted.
While in this state the processor is limited in its ability to respond to input. It is incapable of
latching any interrupts, servicing snoop transactions from symmetric bus masters or responding to
FLUSH# or BINIT# assertions. While the processor is in the Quick Start state, it will not respond
properly to any input signal other than STPCLK#, RESET#, or BPRI#. If any other input signal
changes, then the behavior of the processor will be unpredictable. No serial interrupt messages
may begin or be in progress while the processor is in the Quick Start state.
latching any interrupts, servicing snoop transactions from symmetric bus masters or responding to
FLUSH# or BINIT# assertions. While the processor is in the Quick Start state, it will not respond
properly to any input signal other than STPCLK#, RESET#, or BPRI#. If any other input signal
changes, then the behavior of the processor will be unpredictable. No serial interrupt messages
may begin or be in progress while the processor is in the Quick Start state.
RESET# assertion will cause the processor to immediately initialize itself, but the processor will
stay in the Quick Start state after initialization until STPCLK# is deasserted.
stay in the Quick Start state after initialization until STPCLK# is deasserted.
2.2.6
HALT/Grant Snoop State
The processor will respond to snoop transactions on the system bus while in the Auto Halt, Stop
Grant, or Quick Start state. When a snoop transaction is presented on the system bus the processor
will enter the HALT/Grant Snoop state. The processor will remain in this state until the snoop has
been serviced and the system bus is quiet. After the snoop has been serviced, the processor will
return to its previous state. If the HALT/Grant Snoop state is entered from the Quick Start state,
then the input signal restrictions of the Quick Start state still apply in the HALT/Grant Snoop
state, except for those signal transitions that are required to perform the snoop.
Grant, or Quick Start state. When a snoop transaction is presented on the system bus the processor
will enter the HALT/Grant Snoop state. The processor will remain in this state until the snoop has
been serviced and the system bus is quiet. After the snoop has been serviced, the processor will
return to its previous state. If the HALT/Grant Snoop state is entered from the Quick Start state,
then the input signal restrictions of the Quick Start state still apply in the HALT/Grant Snoop
state, except for those signal transitions that are required to perform the snoop.
2.2.7 Sleep
State
The Sleep state is a very low-power state in which the processor maintains its context and the
phase-locked loop (PLL) maintains phase lock. The Sleep state can only be entered from the Stop
Grant state. After entering the Stop Grant state, the SLP# signal can be asserted, causing the
processor to enter the Sleep state. The SLP# signal is not recognized in the Normal or Auto Halt
states.
phase-locked loop (PLL) maintains phase lock. The Sleep state can only be entered from the Stop
Grant state. After entering the Stop Grant state, the SLP# signal can be asserted, causing the
processor to enter the Sleep state. The SLP# signal is not recognized in the Normal or Auto Halt
states.