Intel E3-1105C AV8062701048800 データシート
製品コード
AV8062701048800
Electrical Specifications
Intel
®
Xeon
®
and Intel
®
Core™ Processors For Communications Infrastructure
Datasheet - Volume 1 of 2
May 2012
114
Document Number: 327405
-
001
9.13
Signal Quality
Data transfer requires the clean reception of data signals and clock signals. Ringing
below receiver thresholds, non-monotonic signal edges, and excessive voltage swings
will adversely affect system timings. Ringback and signal non-monotonically cannot be
tolerated since these phenomena may inadvertently advance receiver state machines.
Excessive signal swings (overshoot and undershoot) are detrimental to silicon gate
oxide integrity, and can cause device failure if absolute voltage limits are exceeded.
Overshoot and undershoot can also cause timing degradation due to the build up of
inter-symbol interference (ISI) effects.
For these reasons, it is crucial that the designer work towards a solution that provides
acceptable signal quality across all systematic variations encountered in volume
manufacturing.
This section documents signal quality metrics used to derive topology and routing
guidelines through simulation. All specifications are specified at the processor die (pad
measurements).
Specifications for signal quality are for measurements at the processor core only and
are only observable through simulation. Therefore, proper simulation is the only way to
verify proper timing and signal quality.
Figure 9-10. Test Reset (TRST#), Async Input, and PROCHOT# Timing Waveform
Figure 9-11. THERMTRIP# Power Down Sequence
T18 (TRST# Pulse Width)
V
T
q
=
Tq
T1 (Async CMOS Pulse Width)
T4 (PROCHOT# Pulse Width)
THERMTRIP#
Vcc
T
A
T
A
= T5: THERMTRIP# assertion until V
CC
removal