Intel E3-1105C AV8062701048800 データシート
製品コード
AV8062701048800
Thermal Management
Intel
®
Xeon
®
and Intel
®
Core™ Processors For Communications Infrastructure
May 2012
Datasheet - Volume 1 of 2
Document Number: 327405
-
001
65
If a processor load-based Enhanced Intel SpeedStep Technology/P-state transition
(through MSR write) is initiated while the Adaptive Thermal Monitor is active, there are
two possible outcomes:
• If the P-state target frequency is higher than the processor core optimized target
frequency, the p-state transition is deferred until the thermal event has been
completed.
• If the P-state target frequency is lower than the processor core optimized target
frequency, the processor transitions to the P-state operating point.
7.3.1.1.2
Clock Modulation
If the frequency/voltage changes are unable to end an Adaptive Thermal Monitor
event, the Adaptive Thermal Monitor utilizes clock modulation. Clock modulation is
done by alternately turning the clocks off and on at a duty cycle (ratio between clock
“on” time and total time) specific to the processor. The duty cycle is factory configured
to 25% on and 75% off and cannot be modified. The period of the duty cycle is
configured to 32 microseconds when the TCC is active. Cycle times are independent of
processor frequency. A small amount of hysteresis has been included to prevent
excessive clock modulation when the processor temperature is near its maximum
operating temperature. Once the temperature has dropped below the maximum
operating temperature, and the hysteresis timer has expired, the TCC goes inactive and
clock modulation ceases. Clock modulation is automatically engaged as part of the TCC
activation when the frequency/voltage targets are at their minimum settings. Processor
performance decreases by the same amount as the duty cycle when clock modulation is
active. Snooping and interrupt processing are performed in the normal manner while
the TCC is active.
7.3.1.2
Digital Thermal Sensor
Each processor execution core has an on-die Digital Thermal Sensor (DTS) which
detects the core’s instantaneous temperature. The DTS is the preferred method of
monitoring processor die temperature because
• It is located near the hottest portions of the die.
• It can accurately track the die temperature and ensure that the Adaptive Thermal
• It can accurately track the die temperature and ensure that the Adaptive Thermal
Monitor is not excessively activated.
Temperature values from the DTS can be retrieved through
• A software interface via processor Model Specific Register (MSR).
• A processor hardware interface as described in
• A processor hardware interface as described in
.
Note:
When temperature is retrieved by processor MSR, it is the instantaneous temperature
of the given core. When temperature is retrieved via PECI, it is the average of the
highest DTS temperature in the package over a 256 ms time window. Intel
recommends using the PECI reported temperature for platform thermal control that
benefits from averaging, such as fan speed control. The average DTS temperature may
not be a good indicator of package Adaptive Thermal Monitor activation or rapid
increases in temperature that triggers the Out of Specification status bit within the
PACKAGE_THERM_STATUS MSR 01B1h and IA32_THERM_STATUS MSR 19Ch.
Code execution is halted in C1-C7. Therefore temperature cannot be read via the
processor MSR without bringing a core back into C0. However, temperature can still be
monitored through PECI in lower C-states except for C7.