Intel E3-1105C AV8062701048800 データシート

Intel

製品コード

AV8062701048800

Intel

®

Xeon

®

and Intel

®

Core™ Processors For Communications Infrastructure

May 2012

Datasheet - Volume 1 of 2

Document Number: 327405-001

7

Contents

PCI Express* PCI Port Bifurcation ......................................................................... 33

PCIe* Typical Operation 16 Lanes Mapping ............................................................ 34

Power States ..................................................................................................... 47

Idle Power Management Breakdown of the Processor Cores ..................................... 50

Thread and Core C-State Entry and Exit ................................................................ 51

Package C-State Entry and Exit............................................................................ 55

Frequency and Voltage Ordering........................................................................... 64

Example of PECI Host-Client Connection.............................................................. 100

Input Device Hysteresis .................................................................................... 101

Differential Clock – Differential Measurements...................................................... 110

Differential Clock – Single Ended Measurements ................................................... 111

DDR3 Command / Control and Clock Timing Waveform ......................................... 111

DDR3 Receiver Eye Mask................................................................................... 112

DDR3 Clock to DQS Skew Timing Waveform ........................................................ 112

PCI Express* Receiver Eye Margins..................................................................... 113

TAP Valid Delay Timing Waveform ...................................................................... 113

Test Reset (TRST#), Async Input, and PROCHOT# Timing Waveform ...................... 114

THERMTRIP# Power Down Sequence .................................................................. 114

VCC Overshoot Example Waveform..................................................................... 116

Maximum Acceptable Overshoot/Undershoot Waveform......................................... 117

Ball Map (Bottom View, Upper Left Side) ............................................................. 142

Ball Map (Bottom View, Upper Right Side) ........................................................... 143

Ball Map (Bottom View, Lower Left Side) ............................................................. 144

Ball Map (Bottom View, Lower Right Side) ........................................................... 145

Processor 4-Core Die Mechanical Package............................................................ 147

Processor 2-Core Die / 1-Core Die Mechanical Package.......................................... 148

Tables

Processor Documents ......................................................................................... 11

Cave Creek PCH Documents ................................................................................ 12

Public Specifications ........................................................................................... 12

Terminology ...................................................................................................... 13

Supported UDIMM Module Configurations

......................................................... 24

Supported SO-DIMM Module Configurations

1

...................................................... 25

Supported Memory Down Configurations 1 ............................................................ 26

DDR3 System Memory Timing Support.................................................................. 27

Hardware Straps for PCIe* Controller Enabling (Port 1 Only) .................................... 35

Hardware Straps for Normal/Reversed Operation of PCIe* Lanes .............................. 36

Reference Clock ................................................................................................. 37

Base Features by SKU......................................................................................... 45

System States ................................................................................................... 48

Processor Core/Package State Support.................................................................. 48

Integrated Memory Controller States .................................................................... 48

PCIe* Link States............................................................................................... 49

DMI States ........................................................................................................ 49

G, S and C State Combinations ............................................................................ 49

Coordination of Thread Power States at the Core Level............................................ 51

P_LVLx to MWAIT Conversion............................................................................... 52

Coordination of Core Power States at the Package Level .......................................... 54

TDP Specifications .............................................................................................. 62

Junction Temperature Specification....................................................................... 62

Signal Description Buffer Types ............................................................................ 71

Memory Channel A ............................................................................................. 71

Memory Channel B ............................................................................................. 72