Intel D2500 DF8064101055400 データシート
製品コード
DF8064101055400
Datasheet - Volume 1 of 2
25
2.7
DDI Audio Interface
LVDS_CTRL_DATA
Display Data Channel data: LVDS I2C backlight
control: Some panels still support this, but most
have gone to using PWM LVDS I2C EDID:
I/O
COD
LVDS_DDC_CLK
LVDS I2C EDID: LVDS Flat Panel I2C Clock and
Data for EDID read and control.
LVDS_DDC_DATA sampled as a pin-strap for
LVDS_DDC_DATA sampled as a pin-strap for
LVDS port presence detect.
I/O
COD
LVDS_DDC_DATA
LVDS Flat Panel I2C Clock and Data for EDID
read and control. I2C based control signal (data)
for External SSC clock chip control.
LVDS_DDC_DATA sampled as a pin-strap for
LVDS_DDC_DATA sampled as a pin-strap for
LVDS port presence detect.
I/O
COD
Table 2-14.DDI Audio Signals (Sheet 1 of 2)
Signal Name
Description
Direction
Type
AZIL_BCLK
Intel HD Audio BCLK: Bit Clock: 24.00-MHz clock
sourced from the controller and connecting to all
codecs on the Link.
I
CMOS
AZIL_RST#
Intel HD Audio Reset: Active low link reset
signal. RST# is sourced from the controller and
connects to all Codecs on the link. Assertion of
RST# results in all link interface logic being reset
to default power on state.
I
CMOS
AZIL_SYNC
Intel HD Audio SYNC: This signal marks input
and output frame boundaries (frame synch) as
well as identifies outbound data streams (stream
tags). SYNC is always sourced from the
controller and connects to all codecs on the link
I
CMOS
Table 2-13.LVDS Signals (Sheet 2 of 2)
Signal Name
Description
Direction
Type