Intel i5-4200H CL8064701470601 データシート

IST_TRIGGER

Signal is for IFDIM testing only.

I

CMOS

IVR_ERROR

Signal is for debug. If both THERMTRIP# and this signal are

simultaneously asserted, the processor has encountered an

unrecoverable power delivery fault and has engaged automatic

shutdown as a result.

O

CMOS

RESET#

Platform Reset pin driven by the PCH.

I

CMOS

RSVD
RSVD_TP
RSVD_NCTF

RESERVED: All signals that are RSVD and RSVD_NCTF must be

left unconnected on the board. Intel recommends that all

RSVD_TP signals have via test points.

No Connect

Test Point

Non-Critical to

Function

SM_DRAMRST#

DRAM Reset: Reset signal from processor to DRAM devices. One

signal common to all channels.

O

CMOS

TESTLO_x

TESTLO should be individually connected to V

SS

 through a

resistor.

PEG_RCOMP

PCI Express Resistance Compensation

I

A

PEG_RXP[15:0]
PEG_RXN[15:0]

PCI Express Receive Differential Pair

I

PCI Express

PEG_TXP[15:0]
PEG_TXN[15:0]

PCI Express Transmit Differential Pair

O

PCI Express

eDP_TXP[1:0]
eDP_TXN[1:0]

embedded DisplayPort Transmit Differential Pair

O

eDP

eDP_AUXP
eDP_AUXN

embedded DisplayPort Auxiliary Differential Pair

O

eDP

eDP_HPD

embedded DisplayPort Hot-Plug Detect. The

polarity of this signal is active low.

I

A

eDP_RCOMP

embedded DisplayPort Current Compensation

I/O

A

eDP_DISP_UTIL

Low voltage multipurpose DISP_UTIL pin on the

processor for backlight modulation control of

embedded panels and S3D device control for active

shutter glasses. This pin will co-exist with

functionality similar to existing BKLTCTL pin on the

PCH.

O

Asynchronous CMOS

Mobile 4th Generation Intel

®

 Core

™

 Processor Family, Mobile Intel

®

 Pentium

®

 Processor Family, and Mobile Intel

®

 Celeron

®

Processor Family

July 2014

Datasheet – Volume 1 of 2

Order No.: 328901-007

87