Intel C2530 FH8065401488915 データシート
製品コード
FH8065401488915
Volume 2—SoC Reset and Power Supply Sequences—C2000 Product Family
Reset Sequences and Power-Down Sequences
Intel
®
Atom™ Processor C2000 Product Family for Microserver
Datasheet, Vol. 2 of 3
September 2014
140
Order Number: 330061-002US
Note:
1.
The Min parameter allows satisfying the 30-µs minimum requirement show in Figure 9: Timing for
Entering and Exiting the Power Down of the Intel Low Pin Count (LPC) Interface Specification, Revision
1.1
.
7.2.2.1
SPD Reset Sequence
After power-up, the BIOS might detect the DDR3 DIMM/SODIMM SDRAM frequency
through Serial Presence Detect (SPD) using the SMBus interface. In this case, the BIOS
might initiate a Warm Reset to re-generate and re-lock the internal SoC memory-
controller clocks. From a platform board perspective, the SPD Reset sequence is the
same as the Warm Reset sequence.
Table 7-5.
Warm Reset Sequence
Sym
Parameter
Min
Max
Units
Note
Fig
t56
PMU_PLTRST_B asserted by SoC after SUS_STAT_B
asserted by SoC
60
-
µs
1
t35
PMU_PLTRST_B de-asserted after SUS_STAT_B de-
asserted
60
100
µs