Intel C2550 FH8065401488912 データシート
製品コード
FH8065401488912
Intel
®
Atom™ Processor C2000 Product Family for Microserver
September 2014
Datasheet, Vol. 2 of 3
Order Number: 330061-002US
171
Volume 2—System Address Maps—C2000 Product Family
Physical Address Space Map
10.1.1
SoC Transaction Router Memory Map
The SoC transaction router maps the physical address space as follows:
• CPU core to DRAM
• CPU core to I/O device registers mapped to the MMIO memory space
• CPU core to extended PCI registers using the Enhanced Configuration Access
• CPU core to I/O device registers mapped to the MMIO memory space
• CPU core to extended PCI registers using the Enhanced Configuration Access
Mechanism (ECAM)
• Integrated device (I/O APIC) to CPU cores (local APIC interrupts)
Although 64 GB (36 bits) of physical address space is accessible, some MMIO must
exist in 32-bit-address-memory space to allow MMIO access to 32-bit Operating
Systems (OS).
The MMIO area is large and is at least 256 MB to provide the ECAM. So as to not waste
physical DRAM, the DRAM-access hole created by the address range assigned as MMIO,
is re-mapped to memory access requests starting at the 4-GB address. A section DRAM
is moved to start at the fixed 4-GB boundary, leaving a hole below 4 GB for MMIO. This
creates the following distinct memory regions:
• DOS DRAM + Low DRAM
• Low MMIO
• High DRAM
• High MMIO
• Low MMIO
• High DRAM
• High MMIO
.
The values in these two registers must also match those of the 32-bit RTF_BMBOUND
and RTF_BMBOUNDHI registers located in the configuration space at bus 0, device 14,
function 0, offsets 404h and 408h, respectively.