Intel C2518 FH8065501516710 データシート
製品コード
FH8065501516710
Intel
®
Atom™ Processor C2000 Product Family for Microserver
September 2014
Datasheet, Vol. 2 of 3
Order Number: 330061-002US
227
Volume 2—PCI Express Root Ports (RP)—C2000 Product Family
Architectural Overview
12.3.6
Message Signaled Interrupt (MSI) Capability
Supported by the SoC root ports:
• Per-vector masking capable (PVM).
Not Supported by the SoC root ports:
• Address 64-Bit Capable - The root ports are not capable of generating a 64-bit
message address.
• Multiple Message Capable - No, only one message is supported.
Supported by the root ports when enabled by the software [Default]:
• MSI Enable (MSIE) - When set, MSI is enabled and traditional interrupt pins are not
used to generate interrupts. Default is 0 (not set).
• Trigger Mode (TM) - Either Edge-Triggered or Level-Triggered. Default is Edge-
Triggered.
• Level- or edge-triggered messages are always treated as assert messages. For
level-triggered interrupts, the Level bit reflects the interrupt input state if TM
(above) specifies the level-triggered mode as follows:
— 0: Deassert messages
— 1: Assert messages
— 1: Assert messages
12.3.7
Advanced Error Reporting (AER) Capability
PCI Express* defines two error reporting paradigms: the baseline capability and the
Advanced Error Reporting (AER) capability. The baseline error reporting capabilities are
required of all PCI Express devices and define the minimum error reporting
requirements. The SoC root ports provide the optional Advanced Error Reporting
Capability which is defined for more robust error reporting and is implemented with a
specific PCI Express Capability structure.
PCIe* baseline error handling does not support severity programming. The Advanced
Error Reporting Capability provides each of the root ports the Uncorrectable Error
Severity register which allows each uncorrectable error to be programmed to fatal or
non-fatal. Uncorrectable errors are not recoverable using defined PCI Express
mechanisms. However, the SoC considers a particular error fatal to a link or device or
possibly considers that error non-fatal. The Uncorrectable Error Severity register
(ERRUNCSEV) default value is re-programmed if the device driver or platform software
requires more robust error handling.
12.3.8
Access Control Services (ACS) Capability
ACS prevents various forms of silent data corruption by preventing PCI Express
Requests from being incorrectly routed to a peer Endpoint below a switch. ACS is also
used to validate that every request transaction between two downstream components
is allowed. Also, ACS allows some robustness checks by checking for the ReqID from a
function to be a valid ReqID at a coarse granularity. When ACS is enabled, the PCIe
Root Port does loopback memory transactions (reads and writes) to the same port if
the address map check matched.