Intel E3815 FH8065301567411 データシート
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製品コード
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
1004
Datasheet
14.11.342 SPDSTRIDE—Offset 72488h
Sprite D Stride Register
Access Method
Default: 00000000h
14.11.343 SPDPOS—Offset 7248Ch
Sprite D Position Register
Access Method
Default: 00000000h
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
GTTMMADR_LSB Type:
PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference:
GTTMMADR_LSB Reference:
[B:0, D:2, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SPRITE
_D_STRID
E
RES
E
RVE
D
Bit
Range
Default &
Access
Field Name (ID): Description
31:6
0b
RW
SPRITE_D_STRIDE:
This is the stride for Sprite D in bytes. When using linear memory,
this must be 64 byte aligned. When using tiled memory, this must be 256 byte aligned.
This register is updated through a command packet passed through the command
stream or writes to this register. When it is desired to update both this and the start
register, the stride register must be written first because the write to the start register is
the trigger that causes the update of both registers on the next VBLANK event. When
using tiled memory, the actual memory buffer stride is limited to a maximum of 16K
bytes.
5:0
0b
RW
RESERVED:
Reserved.
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
GTTMMADR_LSB Type:
PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference:
GTTMMADR_LSB Reference:
[B:0, D:2, F:0] + 10h