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Intel
E3815
データシート
Intel E3815 FH8065301567411 データシート
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FH8065301567411
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Intel
®
Atom™ Processor E3800 Product Family
Datasheet
19
Table 284
Summary of PWM 1 PCI Configuration Registers—0/30/2..........................4278
Table 285
Summary of PWM 1 Memory Mapped I/O Registers—BAR .........................4287
Table 286
Summary of PCU iLB LPC Port 80h I/O Registers—...................................4292
Table 287
PMC Signals........................................................................................4299
Table 288
Transitions Due to Power Failure ...........................................................4302
Table 289
Transitions Due to Power Button............................................................4303
Table 290
System Power Planes...........................................................................4304
Table 291
Causes of SMI and SCI.........................................................................4307
Table 292
INIT# Assertion Causes .......................................................................4310
Table 293
Summary of PCU iLB PMC Memory Mapped I/O Registers—PMC_BASE_ADDRESS
4311
Table 294
Summary of PCI iLB PMC I/O Registers ..................................................4345
Table 295
Summary of PCU iLB PMC I/O Registers—ACPI_BASE_ADDRESS................4348
Table 296
SPI Signals.........................................................................................4366
Table 297
SPI Flash Regions................................................................................4367
Table 298
Region Size Versus Erase Granularity of Flash Components .......................4368
Table 299
Region Access Control..........................................................................4370
Table 300
Hardware Sequencing Commands and Opcode Requirements ....................4374
Table 301
Recommended Pinout for 8-Pin Serial Flash Device ..................................4377
Table 302
Recommended Pinout for 16-Pin Serial Flash Device.................................4377
Table 303
Summary of PCU SPI for Firmware Memory Mapped I/O Registers—
SPI_BASE_ADDRESS ...........................................................................4381
Table 304
UART Signals ......................................................................................4415
Table 305
Baud Rate Examples ............................................................................4416
Table 306
Register Access List .............................................................................4419
Table 307
Summary of PCU iLB UART I/O Registers— .............................................4420
Table 308
SMBus Signal Names ...........................................................................4430
Table 309
I
2
C Block Read....................................................................................4434
Table 310
Enable for PCU_SMB_ALERT# ...............................................................4436
Table 311
Enables for SMBus Host Events .............................................................4436
Table 312
Enables for the Host Notify Command ....................................................4436
Table 313
Host Notify Format ..............................................................................4437
Table 314
Summary of PCU SMBUS PCI Configuration Registers—0/31/3...................4440
Table 315
Summary of PCU SMBUS Memory Mapped I/O Registers—SMB_Config_MBARL ...
4454
Table 316
Summary of PCU SMBUS I/O Registers—SMB_Config_IOBAR ....................4466
Table 317
iLB Signals .........................................................................................4479
Table 318
NMI Sources .......................................................................................4480
Table 319
Summary of PCU iLB Interrupt Decode and Route Memory Mapped I/O Registers—
ILB_BASE_ADDRESS ...........................................................................4481
Table 320
LPC Signals ........................................................................................4516
Table 321
SERIRQ, Stop Frame Width to Operation Mode Mapping ...........................4520
Table 322
SERIRQ Interrupt Mapping....................................................................4521
Table 323
Summary of PCU iLB Low Pin Count (LPC) Bridge PCI Configuration Registers—0/
31/0..................................................................................................4525
Table 324
Summary of PCU iLB LPC BIOS Control Memory Mapped I/O Registers—
RCRB_BASE_ADDRESS ........................................................................4542
Table 325
RTC Signals ........................................................................................4544
Table 326
Register Bits Reset by ILB_RTC_RST# Assertion ......................................4546
Table 327
I/O Registers Alias Locations.................................................................4547
Table 328
RTC Indexed Registers .........................................................................4548
Table 329
Summary of PCU iLB Real Time Clock (RTC) I/O Registers—......................4549
Table 330
8254 Signals ......................................................................................4551
Table 331
Counter Operating Modes .....................................................................4553
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