Intel E3815 FH8065301567411 データシート
製品コード
FH8065301567411
Graphics, Video and Display
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
409
14.4.1.2.2
Sync Signals
HSYNC and VSYNC signals are digital and conform to TTL signal levels at the connector.
Since these levels cannot be generated internal to the device, external level shifting
buffers are required. These signals can be polarity adjusted and individually disabled in
one of the two possible states. The sync signals should power up disabled in the high
state. No composite sync or special flat panel sync support are included.
Since these levels cannot be generated internal to the device, external level shifting
buffers are required. These signals can be polarity adjusted and individually disabled in
one of the two possible states. The sync signals should power up disabled in the high
state. No composite sync or special flat panel sync support are included.
14.4.1.2.3
VESA/VGA Mode
VESA/VGA mode provides compatibility for pre-existing software that set the display
mode using the VGA CRTC registers. Timings are generated based on the VGA register
values and the timing generator registers are not used.
mode using the VGA CRTC registers. Timings are generated based on the VGA register
values and the timing generator registers are not used.
14.4.1.2.4
Display Data Channel (DDC)
DDC is a standard defined by VESA. Its purpose is to allow communication between the
host system and display. Both configuration and control information can be exchanged
allowing plug-and-play systems to be realized. Support for DDC 1 and 2 is
implemented. The SoC uses the VGA_DDCCLK and VGA_DDCDATA signals to
communicate with the analog monitor. The SoC does not generate these signals at 5 V
so external pull-up resistors and level shifting circuitry should be implemented on the
board.
host system and display. Both configuration and control information can be exchanged
allowing plug-and-play systems to be realized. Support for DDC 1 and 2 is
implemented. The SoC uses the VGA_DDCCLK and VGA_DDCDATA signals to
communicate with the analog monitor. The SoC does not generate these signals at 5 V
so external pull-up resistors and level shifting circuitry should be implemented on the
board.
14.4.2
Digital Display Interfaces
14.4.2.1
Signal Descriptions
See
for additional details.
The signal description table has the following headings:
•
Signal Name: The name of the signal/pin
•
Direction: The buffer direction can be either input, output, or I/O (bidirectional)
•
Platform Power: The reference power plane.
•
Description: A brief explanation of the signal’s function
Table 165. Display Physical Interfaces Signal Names (Sheet 1 of 2)
Signal Name
Direction
Description
HDMI / DVI
DP / eDP
DDI[1,0]_TXP[0]
DDI[1,0]_TXP[1]
DDI[1,0]_TXP[2]
DDI[1,0]_TXP[3]
DDI[1,0]_TXP[1]
DDI[1,0]_TXP[2]
DDI[1,0]_TXP[3]
O
Ports 1,0: Transmit Signals
TMDS[1,0]_DATAP[2]
TMDS[1,0]_DATAP[1]
TMDS[1,0]_DATAP[0]
TMDS[1,0]_CLKP
TMDS[1,0]_DATAP[1]
TMDS[1,0]_DATAP[0]
TMDS[1,0]_CLKP
DP[1,0]_MAINP[0]
DP[1,0]_MAINP[1]
DP[1,0]_MAINP[2]
DP[1,0]_MAINP[3]
DP[1,0]_MAINP[1]
DP[1,0]_MAINP[2]
DP[1,0]_MAINP[3]