Intel E3815 FH8065301567411 データシート
製品コード
FH8065301567411
PCU – Serial Peripheral Interface (SPI)
Intel
®
Atom™ Processor E3800 Product Family
4368
Datasheet
Only two masters can access the 3 regions: The SoC CPU core running BIOS code and
the Trusted Execution Engine. The only required region is Region 0, the Flash
Descriptor. Region 0 must be located in the first sector of Device 0.
the Trusted Execution Engine. The only required region is Region 0, the Flash
Descriptor. Region 0 must be located in the first sector of Device 0.
Flash Regions Sizes
SPI Flash space requirements differ by platform and configuration.
indicates
the space needed in the Flash for each region.
31.2.3
Flash Descriptor
The maximum size of the Flash Descriptor is 4 KB. If the block/sector size of the SPI
Flash device is greater than 4 KB, the Flash descriptor will only use the first 4 KB of the
first block. The Flash descriptor requires its own block at the bottom of memory (00h).
The information stored in the Flash Descriptor can only be written during the
manufacturing process as its read/write permissions must be set to Read only when the
system containing the SoC leaves the manufacturing floor.
Flash device is greater than 4 KB, the Flash descriptor will only use the first 4 KB of the
first block. The Flash descriptor requires its own block at the bottom of memory (00h).
The information stored in the Flash Descriptor can only be written during the
manufacturing process as its read/write permissions must be set to Read only when the
system containing the SoC leaves the manufacturing floor.
The Flash Descriptor is made up of eleven sections as indicated in below figure.
Table 298. Region Size Versus Erase Granularity of Flash Components
Region
Size with 4 KB
Blocks
Size with 8 KB
Blocks
Size with 64 KB
Blocks
Descriptor
4 KB
8 KB
64 KB
BIOS
Varies by Platform
Varies by Platform
Varies by Platform
Trusted Execution Engine
Varies by Platform
Varies by Platform
Varies by Platform