Intel E3815 FH8065301567411 データシート
製品コード
FH8065301567411
PCU – iLB – Low Pin Count (LPC) Bridge
Intel
®
Atom™ Processor E3800 Product Family
4520
Datasheet
35.2.7.3
Data Frames
Once the Start frame has been initiated, the ILB_LPC_SERIRQ peripherals start
counting frames based on the rising edge of ILB_LPC_SERIRQ. Each of the IRQ/DATA
frames has exactly 3 phases of 1 clock each:
counting frames based on the rising edge of ILB_LPC_SERIRQ. Each of the IRQ/DATA
frames has exactly 3 phases of 1 clock each:
•
Sample Phase: During this phase, a device drives ILB_LPC_SERIRQ low if its
corresponding interrupt signal is low. If its corresponding interrupt is high, then the
ILB_LPC_SERIRQ devices tri-state ILB_LPC_SERIRQ. ILB_LPC_SERIRQ remains
high due to pull-up resistors.
corresponding interrupt signal is low. If its corresponding interrupt is high, then the
ILB_LPC_SERIRQ devices tri-state ILB_LPC_SERIRQ. ILB_LPC_SERIRQ remains
high due to pull-up resistors.
•
Recovery Phase: During this phase, a device drives ILB_LPC_SERIRQ high if it
was driven low during the Sample Phase. If it was not driven during the sample
phase, it remains tri-stated in this phase.
was driven low during the Sample Phase. If it was not driven during the sample
phase, it remains tri-stated in this phase.
•
Turn-around Phase: The device tri-states ILB_LPC_SERIRQ.
35.2.7.4
Stop Frame
After the data frames, a Stop Frame will be driven by the interrupt controller.
ILB_LPC_SERIRQ will be driven low for two or three LPC clocks. The number of clocks is
determined by the SCNT.MD register bit. The number of clocks determines the next
mode, as indicated in
ILB_LPC_SERIRQ will be driven low for two or three LPC clocks. The number of clocks is
determined by the SCNT.MD register bit. The number of clocks determines the next
mode, as indicated in
35.2.7.5
Serial Interrupts Not Supported
There are four interrupts on the serial stream which are not supported by the interrupt
controller. These interrupts are:
controller. These interrupts are:
•
IRQ0: Heartbeat interrupt generated off of the internal 8254 counter 0.
•
IRQ8: RTC interrupt can only be generated internally.
•
IRQ13: This interrupt (floating point error) is not supported.
•
IRQ14: Interrupt can only be generated by the SATA controller in Legacy mode.
The interrupt controller will ignore the state of these interrupts in the stream.
35.2.7.6
Data Frame Format and Issues
Table below shows the format of the data frames. The decoded INT[A:D]# values are
ANDed with the corresponding PCI-express input signals (PIRQ[A:D]#). This way, the
interrupt can be shared.
ANDed with the corresponding PCI-express input signals (PIRQ[A:D]#). This way, the
interrupt can be shared.
Table 321. SERIRQ, Stop Frame Width to Operation Mode Mapping
Stop Frame
Width
Next Mode
Two LPC clocks
Quiet Mode: Any SERIRQ device initiates a Start Frame
Three LPC clocks
Continuous Mode: Only the interrupt controller initiates a Start
Frame
Frame