Intel N2820 FH8065301616603 データシート
製品コード
FH8065301616603
PCU - iLB – Low Pin Count (LPC) Bridge
1212
Datasheet
25.6.3
Status (PCIE_REG_STATUS)—Offset 6h
The Status register is used to record status information for PCI bus related events.
Reads to this register behave normally. Writes are slightly different in that bits can be
reset, but not set. A one bit is reset (if it is not read-only) whenever the register is
written, and the write data in the corresponding bit location is a 1. For instance, to
clear bit 14 and not affect any other bits, write the value 0100_0000_0000_0000b to
the register.
Access Method
Default: 0210h
7
0b
RO
Wait Cycle Control (WCC): Reserved as '0' per PCI-Express spec
6
0b
RW
Parity Error Response Enable (PERE): This bit controls the device's response to
parity errors. When the bit is set, the device must take its normal action when a parity
error is detected. When the bit is 0, the device sets its Detected Parity Error status bit
(bit 15 in the Status register) when an error is detected, but does not assert PERR# and
continues normal operation.
5
0b
RO
VGA Palette Snoop (VGA_PSE): This bit controls how VGA compatible and graphics
devices handle accesses to VGA palette registers. When this bit is 1, palette snooping is
enabled (that is, the device does not respond to palette register writes and snoops the
data). When the bit is 0, the device should treat palette write accesses like all other
accesses. Reserved as '0' per PCI-Express spec
4
0b
RO
Memory Write and Invalidate Enable (MWIE): This is an enable bit for using the
Memory Write and Invalidate command. When this bit is 1, masters may generate the
command. When it is 0, Memory Write must be used instead. Reserved as '0' per PCI-
Express spec
3
0b
RO
Special Cycle Enable (SCE): Controls a device's action on Special Cycle operations. A
value of 0 causes the device to ignore all Special Cycle operations. A value of 1 allows
the device to monitor Special Cycle operations. Reserved as '0' per PCI-Express spec
2
1b
RO
Bus Master Enable (BME): Controls a device's ability to act as a master on the PCI
bus. A value of 0 disables the device from generating PCI accesses. A value of 1 allows
the device to behave as a bus master. Bus master cannot be disabled on LPC
1
1b
RO
Memory Space Enable (MSE): Controls a device's response to Memory Space
accesses. A value of 0 disables the device response. A value of 1 allows the device to
respond to Memory Space accesses. Memory space cannot be disable on LPC
0
1b
RO
I/O Space Enable (IOSE): Controls a device's response to I/O Space accesses. A
value of 0 disables the device response. A value of 1 allows the device to respond to I/O
Space accesses. I/O space cannot be disable on LPC
Bit
Range
Default &
Access
Description
Type: PCI Configuration Register
(Size: 16 bits)
PCIE_REG_STATUS: [B:0, D:31, F:0] + 6h
15
12
8
4
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
DP
E
SS
E
RM
A
RT
A
ST
A
DT
S
DPD
FBC
RSV
D
0
C66
CLIST
IS
RSV
D
1
Bit
Range
Default &
Access
Description
15
0b
RW
Detected Parity Error (DPE): This bit must be set by the device whenever it detects a
parity error, even if parity error handling is disabled (as controlled by bit 6 in the
Command register).