Intel N2820 FH8065301616603 データシート

製品コード

FH8065301616603

Datasheet

Register Access Methods

3.5.1

PCI Configuration Access – CAM: IO Indexed Scheme

Accesses to configuration space using the IO method relies on two 32-bit IO registers:

•

CONFIG_ADDRESS – IO Port CF8h

•

CONFIG_DATA – IO Port CFCh

These two registers are both 32-bit registers in IO space. Using this indirect access
mode, software uses CONFIG_ADDRESS (CF8h) as an index register, indicating which
configuration space register to access, and CONFIG_DATA (CFCh) acts as a window to
the register pointed to in CONFIG_ADDRESS. Accesses to CONFIG_ADDRESS (CF8h)
are internally captured. Upon a read or write access to CONFIG_DATA (CFCh),
configuration cycles will be generated to the PCI function specified by the address
captured in CONFIG_ADDRESS. The format of the address is shown in the following
table.

Note:

Bit 31 of CONFIG_ADDRESS must be set for a configuration cycle to be generated.

Pseudo code for a PCI register read is shown below:

•

MyCfgAddr[23:16] = bus; MyCfgAddr[15:11] = device; MyCfgAddr[10:8] = funct;

•

MyCfgAddr[7:2] = dWordMask(offset); MyCfgAddr[31] = 1;

•

IOWRITE(0xCF8, MyCfgAddr)

•

Register_Snapshot = IOREAD(0xCFC)

3.5.2

PCI Configuration Access – ECAM: Memory Mapped

Scheme

A flat, 256 MiB memory space may also be allocated to perform configuration
transactions. This is enabled through the BUNIT.BECREG message bus register
(Port: 3h, Register: 27h) found in the Processor Transaction Router. BUNIT.BECREG
allows remapping this 256 MiB region anywhere in physical memory space. Memory
accesses within the programmed MMIO range result in configuration cycles to the
appropriate PCI devices specified by the memory address as shown in the following
table.

Table 29. PCI CONFIG_ADDRESS Register (IO PORT CF8h) Mapping

Field

CONFIG_ADDRESS Bits

Enable PCI Configuration Space Mapping

Reserved