Texas Instruments TMS320DM644x ユーザーズマニュアル
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4.5
MMC Interrupt Mask Register (MMCIM)
Registers
The MMC interrupt mask register (MMCIM) is used to enable (bit = 1) or disable (bit = 0) status interrupts.
If an interrupt is enabled, the transition from 0 to 1 of the corresponding interrupt bit in the MMC status
register 0 (MMCST0) can cause an interrupt signal to be sent to the CPU.
If an interrupt is enabled, the transition from 0 to 1 of the corresponding interrupt bit in the MMC status
register 0 (MMCST0) can cause an interrupt signal to be sent to the CPU.
The MMC interrupt mask register (MMCIM) is shown in
and described in
.
Figure 22. MMC Interrupt Mask Register (MMCIM)
31
16
Reserved
R-0
15
13
12
11
10
9
8
Reserved
ETRNDNE
EDATED
EDRRDY
EDXRDY
Reserved
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R-0
7
6
5
4
3
2
1
0
ECRCRS
ECRCRD
ECRCWR
ETOUTRS
ETOUTRD
ERSPDNE
EBSYDNE
EDATDNE
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10. MMC Interrupt Mask Register (MMCIM) Field Descriptions
Bit
Field
Value
Description
31-13
Reserved
0
Reserved
12
ETRNDNE
Transfer done (TRNDNE) interrupt enable.
0
Transfer done interrupt is disabled.
1
Transfer done interrupt is enabled.
11
EDATED
DAT3 edge detect (DATED) interrupt enable.
0
DAT3 edge detect interrupt is disabled.
1
DAT3 edge detect interrupt is enabled.
10
EDRRDY
Data receive register ready (DRRDY) interrupt enable.
0
Data receive register ready interrupt is disabled.
1
Data receive register ready interrupt is enabled.
9
EDXRDY
Data transmit register (MMCDXR) ready interrupt enable.
0
Data transmit register ready interrupt is disabled.
1
Data transmit register ready interrupt is enabled.
8
Reserved
0
Reserved
7
ECRCRS
Response CRC error (CRCRS) interrupt enable.
0
Response CRC error interrupt is disabled.
1
Response CRC error interrupt is enabled.
6
ECRCRD
Read-data CRC error (CRCRD) interrupt enable.
0
Read-data CRC error interrupt is disabled.
1
Read-data CRC error interrupt is enabled.
5
ECRCWR
Write-data CRC error (CRCWR) interrupt enable.
0
Write-data CRC error interrupt is disabled.
1
Write-data CRC error interrupt is disabled.
4
ETOUTRS
Response time-out event (TOUTRS) interrupt enable.
0
Response time-out event interrupt is disabled.
1
Response time-out event interrupt is enabled.
46
Multimedia Card (MMC)/Secure Digital (SD) Card Controller
SPRUE30B – September 2006