Motorola Espresso Maker MC68340 ユーザーズマニュアル
5- 96
MC68340 USER’S MANUAL
MOTOROLA
CLOCK
1
2
3
4
5
6
7
8
9
0
1
2
3
4
BUS
CONTROLLER
INSTRUCTION
CONTROLLER
CONTROLLER
EXECUTION
TIME
1 PRE-
FETCH
FETCH
CMP
D1,D0
MOVEQ
MOVEQ
#7,D1
BLE.B NOT TAKEN
OFFSET
CALC
WRITE
FOR 4
3 PRE-
FETCH
FETCH
4 PRE-
FETCH
FETCH
NOT
TAKEN
WRITE
FOR 4
MOVE TO
(A0)
MOVE.L D1,(AO)
CMP
2 PRE-
FETCH
FETCH
Figure 5-35. Example 2—Branch Not Taken
5.7.2.3 TIMING EXAMPLE 3—NEGATIVE TAILS. This example (see Figure 5-36) shows
how to use negative tail figures for branches and other change-of-flow instructions. In this
example, bus speed is assumed to be four clocks per access. Instruction three is at the
branch destination.
how to use negative tail figures for branches and other change-of-flow instructions. In this
example, bus speed is assumed to be four clocks per access. Instruction three is at the
branch destination.
Although the CPU32 has a two-word instruction pipeline, internal delay causes minimum
branch instruction time to be three bus cycles. The negative tail is a reminder that an extra
two clocks are available for prefetching a third word on a fast bus; on a slower bus, there
is no extra time for the third word.
branch instruction time to be three bus cycles. The negative tail is a reminder that an extra
two clocks are available for prefetching a third word on a fast bus; on a slower bus, there
is no extra time for the third word.
Instructions
MOVEQ
#7, D1
BRA.W
FARAWAY
MOVE.L
D1, D0
CLOCK
1
2
3
4
5
6
7
8
9
0
1
2
3
4
BUS
CONTROLLER
INSTRUCTION
CONTROLLER
CONTROLLER
EXECUTION
TIME
MOVEQ
OFFSET
CALC
5
6
7
8
9
BRANCH OFFSET
BRA.W FARAWAY
TAKEN
TAKEN
FETCH MOVE.L
FETCH NEXT
INSTRUCTION
PREFETCH
MOVE
TO D0
TO D0
MOVE.L D1,D0
MOVEQ #7,D1
Figure 5-36. Example 3—Branch Negative Tail
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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