Motorola Espresso Maker MC68340 ユーザーズマニュアル
MOTOROLA
MC68340 USER’S MANUAL
8- 13
causes the counter to reload with $FFFF. TOUTx transitions at timeout or is disabled as
programmed by the CR OCx bits. The SR OUT bit reflects the level on TOUTx.
programmed by the CR OCx bits. The SR OUT bit reflects the level on TOUTx.
To determine the number of cycles counted, the value in the CNTR must be read,
inverted, and incremented by 1 (the first count is $FFFF which, in effect, includes a count
of zero). The counter counts in a true 216 fashion. For measuring pulses of even greater
duration, the value in the POx bits in the SR is readable and can be thought of as an
extension of the least significant bits in the CNTR.
inverted, and incremented by 1 (the first count is $FFFF which, in effect, includes a count
of zero). The counter counts in a true 216 fashion. For measuring pulses of even greater
duration, the value in the POx bits in the SR is readable and can be thought of as an
extension of the least significant bits in the CNTR.
NOTE
Once the timer has been enabled, do not clear the SR TG bit
until the pulse has been measured and
until the pulse has been measured and
TGATE
≈
has been
negated.
8.3.6 Period Measurement
This mode is used to count the period of a particular event. The event is defined by the
assertion, negation, and subsequent reassertion of
assertion, negation, and subsequent reassertion of
TGATE
≈
. When
TGATE
≈
is asserted,
the counter begins counting down from $FFFF. The negation of
TGATE
≈
has no effect on
the counter. When
TGATE
≈
is reasserted, the counter stops counting and holds the value
at which it stopped. Further assertions and negations of
TGATE
≈
have no effect on the
counter. This mode can be selected by programming the CR MODEx bits to 101.
The timer is enabled by setting the SWR, CPE, and the TGE bits in the CR. The assertion
of
of
TGATE
≈
starts the counter. When the timer is enabled, the SR ON bit is set. On the
next falling edge of the counter clock, the counter is loaded with the value of $FFFF. With
each successive falling edge of the counter clock, the counter decrements. The PREL1
and PREL2 registers are not used in this mode.
each successive falling edge of the counter clock, the counter decrements. The PREL1
and PREL2 registers are not used in this mode.
The first negation of
TGATE
≈
is ignored, but on the second assertion of
TGATE
≈
, the SR
TG bit is set, the SR ON bit is negated, and the prescaler and counter are disabled.
Subsequent transitions on
Subsequent transitions on
TGATE
≈
do not re-enable the counter. See Figure 8-9 for a
depiction of this mode. The SR TGL bit reflects the level of
TGATE
≈
at all times.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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