Motorola Espresso Maker MC68340 ユーザーズマニュアル
9- 4
MC68340 USER’S MANUAL
MOTOROLA
Table 9-1. Boundary Scan Control Bits
Name
Bit Number
Name
Bit Number
Name
Bit Number
tout2.ctl
29
cs0.ctl
66
ab28.ctl
95
irq7.ctl
52
ab.ctl
83
ab29.ctl
97
irq6.ctl
54
berr.ctl
84
ab30.ctl
99
irq5.ctl
56
db.ctl
85
ab31.ctl
101
cs3.ctl
58
ab24.ctl
87
modck.ctl
122
irq3.ctl
60
ab25.ctl
89
ifetch.ctl
125
cs2.ctl
62
ab26.ctl
91
tout1.ctl
130
cs1.ctl
64
ab27.ctl
93
Boundary scan bit definitions are shown in Table 9-2. The first column in Table 9-2 defines
the bit's ordinal position in the boundary scan register. The shift register bit nearest TDO
(i.e., first to be shifted out) is defined as bit 0; the last bit to be shifted out is 131.
the bit's ordinal position in the boundary scan register. The shift register bit nearest TDO
(i.e., first to be shifted out) is defined as bit 0; the last bit to be shifted out is 131.
The second column references one of the five MC68340 cell types depicted in Figures
9-3–9-7, which describe the cell structure for each type.
9-3–9-7, which describe the cell structure for each type.
The third column lists the pin name for all pin-related bits or defines the name of
bidirectional control register bits. The active level of the control bits (i.e., output driver on)
is defined by the last digit of the cell type listed for each control bit. For example, the
active-high level for irq7.ctl (bit 52) is logic zero since the cell type is IO.Ctl0. The active
level for ab.ctl (bit 83) is logic one, since the cell type is IO.Ctl1. IO.Ctl0 (see Figure 9-6)
differs from IO.Ctl1 (see Figure 9-5) by an inverter in the output enable path.
bidirectional control register bits. The active level of the control bits (i.e., output driver on)
is defined by the last digit of the cell type listed for each control bit. For example, the
active-high level for irq7.ctl (bit 52) is logic zero since the cell type is IO.Ctl0. The active
level for ab.ctl (bit 83) is logic one, since the cell type is IO.Ctl1. IO.Ctl0 (see Figure 9-6)
differs from IO.Ctl1 (see Figure 9-5) by an inverter in the output enable path.
The fourth column lists the pin type: TS-Output indicates a three-state output pin, I/O
indicates a bidirectional pin, and OD-I/O denotes an open-drain bidirectional pin. An open-
drain output pin has two states: off (high impedance) and logic zero.
indicates a bidirectional pin, and OD-I/O denotes an open-drain bidirectional pin. An open-
drain output pin has two states: off (high impedance) and logic zero.
The last column indicates the associated boundary scan register control bit for
bidirectional, three-state, and open-drain output pins.
bidirectional, three-state, and open-drain output pins.
Bidirectional pins include a single scan bit for data (IO.Cell) as depicted in Figure 9-7.
These bits are controlled by one of the two bits shown in Figures 9-5 and 9-6. The value of
the control bit determines whether the bidirectional pin is an input or an output. One or
more bidirectional data bits can be serially connected to a control bit as shown in Figure 9-
8. Note that, when sampling the bidirectional data bits, the bit data can be interpreted only
after examining the IO control bit to determine pin direction.
These bits are controlled by one of the two bits shown in Figures 9-5 and 9-6. The value of
the control bit determines whether the bidirectional pin is an input or an output. One or
more bidirectional data bits can be serially connected to a control bit as shown in Figure 9-
8. Note that, when sampling the bidirectional data bits, the bit data can be interpreted only
after examining the IO control bit to determine pin direction.
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Freescale Semiconductor, Inc.
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