Texas TMS320C645X ユーザーズマニュアル
www.ti.com
Interrupt Conditions
Table 26. Interrupt Source Configuration Options
Field
Access
Reset Value
Value
Function
ICSx
R
0
0b
Condition not present
1b
Condition present
ICCx
W
0
0b
No effect
1b
Condition status cleared
Figure 43. DOORBELL0 Interrupt Registers for Direct I/O Transfers
DOORBELL0 Interrupt Condition Status Registers (ICSR) (Address Offset 0x0200)
31
16
Reserved
R-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ICS15
ICS14
ICS13
ICS12
ICS11
ICS10
ICS9
ICS8
ICS7
ICS6
ICS5
ICS4
ICS3
ICS2
ICS1
ICS0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R = Read, W = Write, n = value at reset
DOORBELL0 Interrupt Condition Clear Registers (ICCR) (Address Offset 0x0208)
31
16
Reserved
R-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ICC15
ICC14
ICC13
ICC12
ICC11
ICC10
ICC9
ICC8
ICC7
ICC6
ICC5
ICC4
ICC3
ICC2
ICC1
ICC0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
LEGEND: R = Read, W = Write, n = value at reset
Where ICS0 - Doorbell0, bit 0 through ICS15 - Doorbell0, bit 15.
Figure 44. DOORBELL1 Interrupt Registers for Direct I/O Transfers
DOORBELL1 Interrupt Condition Status Registers (ICSR) (Address Offset 0x0210)
31
16
Reserved
R-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ICS15
ICS14
ICS13
ICS12
ICS11
ICS10
ICS9
ICS8
ICS7
ICS6
ICS5
ICS4
ICS3
ICS2
ICS1
ICS0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R = Read, W = Write, n = value at reset
DOORBELL1 Interrupt Condition Clear Registers (ICCR) (Address Offset 0x0218)
31
16
Reserved
R-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ICC15
ICC14
ICC13
ICC12
ICC11
ICC10
ICC9
ICC8
ICC7
ICC6
ICC5
ICC4
ICC3
ICC2
ICC1
ICC0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
LEGEND: R = Read, W = Write, n = value at reset
Serial RapidIO (SRIO)
76
SPRU976 – March 2006