Renesas Stereo System SH7709S ユーザーズマニュアル

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Rev. 5.00, 09/03, page 306 of 760
T
1
T
B2
T
B1
T
B2
T
B1
T
B2
T
B1
T
2
CKIO
A25 to A4
A3 to A0
CSn
RD/
WR
RD
D31 to D0
BS
WAIT
Note:  For a write cycle, a basic bus cycle (write cycle) is performed.
Figure 10.30   Burst ROM Basic Access Timing