Philips 8-bit microcontroller with two-clock 80C51 core UM10109 ユーザーズマニュアル
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
User manual
Rev. 02 — 23 May 2005
98 of 133
Philips Semiconductors
UM10109
P89LPC932A1 User manual
[1]
The Keypad Interrupt must be enabled in order for the settings of the KBMASK register to be effective.
15. Watchdog timer (WDT)
The watchdog timer subsystem protects the system from incorrect code execution by
causing a system reset when it underflows as a result of a failure of software to feed the
timer prior to the timer reaching its terminal count. The watchdog timer can only be reset
by a power-on reset.
causing a system reset when it underflows as a result of a failure of software to feed the
timer prior to the timer reaching its terminal count. The watchdog timer can only be reset
by a power-on reset.
15.1 Watchdog function
The user has the ability using the WDCON and UCFG1 registers to control the run /stop
condition of the WDT, the clock source for the WDT, the prescaler value, and whether the
WDT is enabled to reset the device on underflow. In addition, there is a safety mechanism
which forces the WDT to be enabled by values programmed into UCFG1 either through
IAP or a commercial programmer.
condition of the WDT, the clock source for the WDT, the prescaler value, and whether the
WDT is enabled to reset the device on underflow. In addition, there is a safety mechanism
which forces the WDT to be enabled by values programmed into UCFG1 either through
IAP or a commercial programmer.
The WDTE bit (UCFG1.7), if set, enables the WDT to reset the device on underflow.
Following reset, the WDT will be running regardless of the state of the WDTE bit.
Following reset, the WDT will be running regardless of the state of the WDTE bit.
The WDRUN bit (WDCON.2) can be set to start the WDT and cleared to stop the WDT.
Following reset this bit will be set and the WDT will be running. All writes to WDCON need
to be followed by a feed sequence (see
Following reset this bit will be set and the WDT will be running. All writes to WDCON need
to be followed by a feed sequence (see
). Additional bits in WDCON allow the
user to select the clock source for the WDT and the prescaler.
When the timer is not enabled to reset the device on underflow, the WDT can be used in
‘timer mode’ and be enabled to produce an interrupt (IEN0.6) if desired
‘timer mode’ and be enabled to produce an interrupt (IEN0.6) if desired
The Watchdog Safety Enable bit, WDSE (UCFG1.4) along with WDTE, is designed to
force certain operating conditions at power-up. Refer to
force certain operating conditions at power-up. Refer to
for details.
Table 84:
Keypad Interrupt Mask register (KBMASK - address 86h) bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
KBMASK.7
KBMASK.6
KBMASK.5
KBMASK.4
KBMASK.3
KBMASK.2
KBMASK.1
KBMASK.0
Reset
0
0
0
0
0
0
0
0
Table 85:
Keypad Interrupt Mask register (KBMASK - address 86h) bit description
Bit Symbol
Description
0
KBMASK.0
When set, enables P0.0 as a cause of a Keypad Interrupt.
1
KBMASK.1
When set, enables P0.1 as a cause of a Keypad Interrupt.
2
KBMASK.2
When set, enables P0.2 as a cause of a Keypad Interrupt.
3
KBMASK.3
When set, enables P0.3 as a cause of a Keypad Interrupt.
4
KBMASK.4
When set, enables P0.4 as a cause of a Keypad Interrupt.
5
KBMASK.5
When set, enables P0.5 as a cause of a Keypad Interrupt.
6
KBMASK.6
When set, enables P0.6 as a cause of a Keypad Interrupt.
7
KBMASK.7
When set, enables P0.7 as a cause of a Keypad Interrupt.