National CP3BT26 ユーザーズマニュアル
35
www.national.com
CP3
BT26
RDPROT
The RDPROT field controls the global read
protection mechanism for the on-chip flash
program memory. If a majority of the three
RDPROT bits are clear, the flash program
memory is protected against read access
from the serial debug interface or an external
flash programmer. CPU read access is not af-
fected by the RDPROT bits. If a majority of the
RDPROT bits are set, read access is allowed.
protection mechanism for the on-chip flash
program memory. If a majority of the three
RDPROT bits are clear, the flash program
memory is protected against read access
from the serial debug interface or an external
flash programmer. CPU read access is not af-
fected by the RDPROT bits. If a majority of the
RDPROT bits are set, read access is allowed.
WRPROT
The WRPROT field controls the global write
protection mechanism for the on-chip flash
program memory. If a majority of the three
WRPROT bits are clear, the flash program
memory is protected against write access
from any source and read access from the se-
rial debug interface. If a majority of the WR-
PROT bits are set, write access is allowed.
protection mechanism for the on-chip flash
program memory. If a majority of the three
WRPROT bits are clear, the flash program
memory is protected against write access
from any source and read access from the se-
rial debug interface. If a majority of the WR-
PROT bits are set, write access is allowed.
8.5
FLASH MEMORY INTERFACE
REGISTERS
REGISTERS
There is a separate interface for the program flash and data
flash memories. The same set of registers exist in both in-
terfaces. In most cases they are independent of each other,
but in some cases the program flash interface controls the
interface for both memories, as indicated in the following
sections. Table 16 lists the registers.
flash memories. The same set of registers exist in both in-
terfaces. In most cases they are independent of each other,
but in some cases the program flash interface controls the
interface for both memories, as indicated in the following
sections. Table 16 lists the registers.
Table 15
CPU Reset Behavior
EMPTY
ISPE
Boot Area
Start-Up Operation
Not Empty
ISP
Defined
Device starts in IRE/
ERE mode from
Code Area start
address
Not Empty
ISP
Not
Defined
Device starts in IRE/
ERE mode from
Code Area start
address
Not Empty
No ISP
Don’t Care
Device starts in IRE/
ERE mode from
address 0
Empty
ISP
Defined
Device starts in ISP
mode from Code
Area start address
Empty
ISP
Not
Defined
Device starts in ISP
mode and is kept in
its reset state
Empty
No ISP
Don’t Care
Table 16
Flash Memory Interface Registers
Program
Memory
Data
Memory
Description
FMIBAR
FF F940h
FSMIBAR
FF F740h
Flash Memory
Information Block
Address Register
Address Register
FMIBDR
FF F942h
FSMIBDR
FF F742h
Flash Memory
Information Block
Address Register
Address Register
FM0WER
FF F944h
FF F944h
FSM0WER
FF F744h
Flash Memory 0
Write Enable Register
FM1WER
FF F946h
FF F946h
N/A
Flash Memory 1
Write Enable Register
FMCTRL
FF F94Ch
FSMCTRL
FF F74Ch
Flash Memory
Control Register
FMSTAT
FF F94Eh
FSMSTAT
FF F74Eh
FF F74Eh
Flash Memory
Status Register
FMPSR
FF F950h
FSMPSR
FF F750h
Flash Memory
Prescaler Register
FMSTART
FF F952h
FSMSTART
FF F752h
Flash Memory Start
Time Reload Register
FMTRAN
FF F954h
FSMTRAN
FF F754h
Flash Memory
Transition Time
Reload Register
FMPROG
FF F956h
FF F956h
FSMPROG
FF F756h
Flash Memory
Programming Time
Reload Register
FMPERASE
FF F958h
FSMPERASE
FF F758h
Flash Memory Page
Erase Time Reload
Register
FMMERASE0
FF F95Ah
FSMMERASE0
FF F75Ah
Flash Memory Module
Erase Time Reload
Register 0
FMEND
FF F95Eh
FSMEND
FF F75Eh
Flash Memory End
Time Reload Register
FMMEND
FF F960h
FF F960h
FSMMEND
FF F760h
Flash Memory Module
Erase End Time
Reload Register
Reload Register
FMRCV
FF F962h
FSMRCV
FF F762h
Flash Memory
Recovery Time
Reload Register
FMAR0
FF F964h
FSMAR0
FF F764h
Flash Memory
Auto-Read Register 0
FMAR1
FF F966h
FSMAR1
FF F766h
Flash Memory
Auto-Read Register 1
FMAR2
FF F968h
FSMAR2
FF F768h
Flash Memory
Auto-Read Register 2