National CP3BT26 ユーザーズマニュアル

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3. By extension, the ADC negative voltage reference can

be internally connected to the TSY- terminal, to recover
the full 4096 values.

The Global Configuration Register (ADCGCR) provides the
flexibility to implement any of these techniques.

To reduce the level of switching noise in the environment of
the ADC, it is possible to operate the CP3BT26 in low-power
modes, in which the System Clock is slowed or switched off.
Under these conditions, Auxiliary Clock 2 can be selected
as the clock source for the ADC module, however conver-
sion results cannot be read by the system while the System
Clock is suspended. The expected operation in power-sav-
ing modes is therefore:

1. ADC is configured and a conversion is primed or trig-

gered.

2. A power-saving mode is entered.
3. ADC conversion completes and a wake-up signal is as-

serted to the MIWU unit.

4. Device wakes up and processes the conversion result.

To conserve power, the ADC should be disabled before en-
tering a low-power mode if its function is not required.

The ADC module provides support for an In-System Emula-
tor by means of a special FREEZE input. When FREEZE is
asserted the module will exhibit the following specific be-
havior:

„ The automatic clear-on-read function of the result regis-

ter (ADCRESLT) is disabled.

„ The FIFO is updated as usual, and an interrupt for a

completed conversion can be asserted.

Table 34 lists the ADC registers.

ADCGCR

FF F3C0h

ADC Global

Configuration Register

ADCACR

FF F3C2h

ADC Auxiliary

Configuration Register

ADCCNTRL

FF F3C4h

ADC Conversion

Control Register

ADCSTART

FF F3C6h

ADC Start Conversion

Register

ADCSCDLY

FF F3C8h

ADC Start Conversion

Delay Register

ADCRESLT

FF F3CAh

ADC Result Register