Intel 440GX ユーザーズマニュアル
Intel
®
440GX AGPset Design Guide
4-2
Debug Recommendations
Contact your local Intel Field Sales representative to complete the proper software license
agreement and non-disclosure agreement required to receive the ITP.
agreement and non-disclosure agreement required to receive the ITP.
4.2.3
Bus Functional Model (BFM)
A bus functional model for the Intel
®
Pentium
®
II processor system bus is available from third
party vendors and requires a special non-disclosure agreement. Contact your local Intel Field Sales
representative for information on the bus functional model vendors and to complete the appropriate
non-disclosure agreements.
representative for information on the bus functional model vendors and to complete the appropriate
non-disclosure agreements.
4.2.4
I/O Buffer Models
IBIS Models are available from Intel for:
•
Intel
®
Pentium
®
II processor (QUAD only, IBIS models TBD)
•
82443GX IBIS Models
•
PIIX4E PCI ISA IDE Xcelerator IBIS Models
Contact your local Intel Field Sales representative for a copy of these models and to complete the
appropriate non-disclosure agreements.
appropriate non-disclosure agreements.
4.2.5
FLO
THERM* Model
A FLOTHERM* Model is available for the Intel
®
Pentium
®
II processor.
4.3
Debug Features
These suggestions are for debug purposes only on initial prototype systems, and are not required
for production level systems. Some of these features may be desirable test functions that you may
incorporate onto production boards.
for production level systems. Some of these features may be desirable test functions that you may
incorporate onto production boards.
4.3.1
Intel
®
Pentium
®
II
Processor LAI Issue
Note:
If the LAI562 tool is not being used, this issue can be ignored. However, be aware that if you send
a system to Intel for debug, the absence of the required workarounds will prohibit
debugassistance from Intel.
a system to Intel for debug, the absence of the required workarounds will prohibit
debugassistance from Intel.
To maintain backward compatibility with Intel
®
Pentium
®
II processor, Intel suggests the
following circuitry to be considered. The LAI562 integration tool has been designed such that an
extra load will be presented on the CMOS signals connected to the Slot 1 connector. The following
list of signals are affected:
extra load will be presented on the CMOS signals connected to the Slot 1 connector. The following
list of signals are affected:
PREQ#, TCK, TDI, TDO, TMS, TRST#, INIT#, FLUSH#, STPCLK#, PICCLK, PICD[1:0]#,
LINT[0]/INTR, LINT[1]/NMI, IERR#, SMI#, PWRGOOD, THERMTRIP#, SLP#, FERR#,
IGNNE# and A20M#.
LINT[0]/INTR, LINT[1]/NMI, IERR#, SMI#, PWRGOOD, THERMTRIP#, SLP#, FERR#,
IGNNE# and A20M#.
Figure 4-1
describes the CMOS probe signals of the LAI562.