Intel 440GX ユーザーズマニュアル

Intel

®

 440GX AGPset Design Guide

3-5

Design Checklist

•

Include a circuit for the system bus clock to core frequency ratio to the processor. The ratio 
should be configurable as opposed to hard wired. The bus frequency select straps will be 
latched on the rising edge of CRESET#.

•

CRESET# is used as the selection signal for muxing A20M#, IGNNE#, INTR, and NMI with 
the processor bus/core frequency selection jumpers. A ‘244 buffer maybe used as a mux. The 
outputs of the ‘244 device are fed to open collector buffers for voltage translation to the CPU. 
See the reference board schematics for specific implementation.

•

PICCLK must be driven by a clock even if an I/O APIC is not being used. This clock can be as 
high as 33.3 MHz in a UP system. A DP system utilizing Intel’s I/O APIC (82093AA) has a 
maximum PICCLK frequency of 16.666 MHz.

 Processor Signals

•

Dual termination (56 ohm) to Vtt of the GTL+ bus is required if the trace length restrictions of 
a SET (single-ended termination) environment cannot be met.

•

THERMTRIP# must be pulled-up to Vcc

2.5 

(150 ohm to 10K ohm) if used by system logic. 

The signal may be wire-OR’ed and does not require an external gate. It may be left as NC if it 
is not used. See the Debug Recommendations for further information that may affect the 
resistor values.

•

The FERR# output must be pulled up to Vcc2.5 (150 ohm to 10K ohm) and connected to the 
PIIX4E. The reference schematics uses 220 ohms. See the Debug Recommendations for 
further information that may affect these resistor values.

•

PICD[1:0]# must have 150 ohm pull-ups to Vcc2.5 even if an I/O APIC is not being used. See 
the Debug Recommendations for further information that may affect these resistor values.

•

All CMOS inputs should be pulled up to Vcc2.5 (150 ohm to 10K ohm). See the Debug 
Recommendations for further information that may affect these resistor values.

•

Be sure the Slot 1 inputs are not being driven by 3.3V or 5V logic. Logic translation of 3.3V or 
5V signals may be accomplished by using open-drain drivers pulled-up to Vcc2.5.

•

The PWRGOOD input should be driven to the appropriate level from the active-high “AND” 
of the Power-Good signals from the 5V, 3.3V and Vcc

CORE

 supplies. The output of any logic 

used to drive PWRGOOD should be a Vcc

2.5

 level to the processor. 

•

No V

REF

 should be generated for the Intel

®

 Pentium

®

 II processor. V

REF

 is locally generated 

on the processor card.

•

Vtt must have adequate bulk decoupling based on the reaction time of the regulator used to 
generate Vtt. It must provide for a current ramp of up to 8A/uS while maintaining the voltage 
tolerance defined in the Intel

 II Processor datasheet.

•

If an on-board voltage regulator is used instead of a VRM, Vcc

CORE

 must have adequate bulk 

decoupling based on the reaction time of the regulator used to generate Vcc

CORE

. It must 

provide for a current ramp of up to 30A/uS while maintaining the VRM 8.2 DC-DC Converter 
Specification. 

•

The VID lines should have pull-up resistors ONLY if they are required by the Voltage 
Regulator Module or on board regulator that you have chosen. The pull-up voltage used should 
be to the regulator input voltage (5V or 12V). However, if 12V is used, a resistor divider 
should be utilized to lower the VID signal to CMOS/TTL levels. The VID signals may be used 
to detect the presence of a processor core. A pull-up is not required unless the VID signals are