Elixir DDR2 UDIMM 1024MB M2Y1G64TU88D5B-AC ユーザーズマニュアル
製品コード
M2Y1G64TU88D5B-AC
M2Y1G64TU88D0B / M2Y2G64TU8HD0B / M2Y1G64TU88D4B / M2Y2G64TU8HD4B / M2Y1G64TU88D4B
M2Y1G64TU88D5B / M2Y2G64TU8HD5B / M2Y1G64TU88D6B / M2Y2G64TU8HD6B
M2Y1G64TU88D7B
M2Y1G64TU88D5B / M2Y2G64TU8HD5B / M2Y1G64TU88D6B / M2Y2G64TU8HD6B
M2Y1G64TU88D7B
1GB: 128M x 64 / 2GB: 256M x 64
Unbuffered DDR2 SDRAM DIMM
REV 1.2
7
10/2008
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Serial Presence Detect --
Part 1 of 2 (1GB)
128Mx64 1 RANK UNBUFFERED DDR2 SDRAM DIMM based on 128Mx8, 8Banks, 8K Refresh, 1.8V DDR2 SDRAMs with SPD
Byte
Description
SPD Entry Value
Serial PD Data Entry
(Hexadecimal)
Note
PC2-5300
-3C
PC2-6400
-AC
PC2-5300
-3C
PC2-6400
-AC
0
Number of Serial PD Bytes Written during Production
128
80
1
Total Number of Bytes in Serial PD device
256
08
2
Fundamental Memory Type
DDR2
08
3
Number of Row Addresses on Assembly
14
0E
4
Number of Column Addresses on Assembly
10
0A
5
Number of DIMM Ranks
1 rank, Height=30mm
60
6
Data Width of Assembly
X64
40
7
Reserved
Undefined
00
8
Voltage Interface Level of this Assembly
SSTL_1.8V
05
9
DDR2 SDRAM Device Cycle Time at CL=X
3ns
2.5ns
30
25
10
DDR2 SDRAM Device Access Time from Clock at CL=X
0.45ns
0.4ns
45
40
11
DIMM Configuration Type
Non parity/ECC
00
12
Refresh Rate/Type
7.8
s
82
13
Primary DDR2 SDRAM Width
X8
08
14
Error Checking DDR2 SDRAM Device Width
Undefined
00
15
Reserved
Undefined
00
16
DDR2 SDRAM Device Attributes: Burst Length Supported
4,8
0C
17
DDR2 SDRAM Device Attributes: Number of Device Banks
8
08
18
DDR2 SDRAM Device Attributes: CAS Latencies
Supported
Supported
3,4,5
38
19
DIMM Mechanical Characteristics
x ≤ 4.10 (mm)
01
20
DDR2 SDRAM DIMM Type Information
UDIMM (133.35mm)
02
21
DDR2 SDRAM Module Attributes:
Normal DIMM
00
22
DDR2 SDRAM Device Attributes: General
Support weak driver,
50
ODT, and PASR
07
23
Minimum Clock Cycle at CL=X-1
3.75ns
3D
24
Maximum Data Access Time from Clock at CL=X-1
0.5ns
50
25
Minimum Clock Cycle Time at CL=X-2
5.0ns
50
26
Maximum Data Access Time from Clock at CL=X-2
0.6ns
60
27
Minimum Row Precharge Time (t
RP
)
15ns
12.5ns
3C
32
28
Minimum Row Active to Row Active delay (t
RRD
)
7.5ns
1E
29
Minimum RAS to CAS delay (t
RCD
)
15ns
12.5ns
3C
32
30
Minimum RAS Pulse Width (t
RAS
)
45ns
2D
31
Module Bank Density
1GB
01
32
Address and Command Setup Time Before Clock (t
IS
)
0.20ns
0.17ns
20
17
33
Address and Command Hold Time After Clock (t
IH
)
0.27ns
0.25ns
27
25
34
Data Input Setup Time Before Clock (t
DS
)
0.10ns
0.05ns
10
05
35
Data Input Hold Time After Clock (t
DH
)
0.17ns
0.12ns
17
12
36
Write Recovery Time (t
WR
)
15.0ns
3C
37
Internal Write to Read Command delay (t
WTR
)
7.5ns
1E
38
Internal Read to Precharge delay (t
RTP
)
7.5ns
1E
39
Reserved
Undefined
00