Sundance Spas ST201 ユーザーズマニュアル
2
Sundance Technology
ST201
PRELIMINARY draft 2
BLOCK DIAGRAM
PHYLNKN
RSTN
PCICLK
GNTN
IDSEL
INTAN
WAKE
REQN
AD[31..0]
CBEN[3:0]
PAR
FRAMEN
IRDYN
TRDYN
DEVSELN
STOPN
PERRN
SERRN
VDET
PCI
TXD[3..0]
TXEN
TXCLK
RXD[3..0]
RXCLK
RXER
RXDV
CRS
COL
MDC
MDIO
MII
ED[7..0]
EA[15..0]
EWEN
EOEN
LEDPWRN
LEDLNKN
LEDDPLXN
LEDSPDN
GPIO0
GPIO1
RSTOUT
X25I
X25O
CLK25
VCC
GND
PHYDPLXN
PHYSPDN
EEPROM
EXPANSION ROM
PHY
LED
POWER
MISCELLANEOUS
PCI
Bus
Bus
I/F
Tx
DMA
Tx
FIFO
Rx
FIFO
Rx
DMA
Tx
MAC
Rx
MAC
Status/Control
Registers
Statistic Registers
EEDO
EEDI
EESK
EECS
FIGURE 1: ST201 Block Diagram