Nxp Semiconductors LPC2917 ユーザーズマニュアル

LPC2917_19_1

© NXP B.V. 2007. All rights reserved.

The flash memory has a 128-bit wide data interface and the flash controller offers two 
128-bit buffer lines to improve system performance. The flash has to be programmed 
initially via JTAG. In-system programming must be supported by the boot loader. 
In-application programming is possible. Flash memory contents can be protected by 
disabling JTAG access. Suspension of burning or erasing is not supported.

The key features are:

Programming by CPU via AHB

Programming by external programmer via JTAG

JTAG access protection

Burn-finished and erase-finished interrupt

After reset flash initialization is started, which takes t

init

 time, see 

initialization flash access is not possible and AHB transfers to flash are stalled, blocking 
the AHB bus.

During flash initialization the index sector is read to identify the status of the JTAG access 
protection and sector security. If JTAG access protection is active the flash is not 
accessible via JTAG. ARM debug facilities are disabled to protect the flash-memory 
contents against unwanted reading out externally. If sector security is active only the 
concerned sections are read.

Flash can be read synchronously or asynchronously to the system clock. In synchronous 
operation the flash goes into standby after returning the read data. Started reads cannot 
be stopped, and speculative reading and dual buffering are therefore not supported.

With asynchronous reading, transfer of the address to the flash and of read data from the 
flash is done asynchronously, giving the fastest possible response time. Started reads can 
be stopped, so speculative reading and dual buffering are supported.

Buffering is offered because the flash has a 128-bit wide data interface while the AHB 
interface has only 32 bits. With buffering a buffer line holds the complete 128-bit flash 
word, from which four words can be read. Without buffering every AHB data port read 
starts a flash read. A flash read is a slow process compared to the minimum AHB cycle 
time, so with buffering the average read time is reduced. This can improve system 
performance.

With single buffering the most recently read flash word remains available until the next 
flash read. When an AHB data-port read transfer requires data from the same flash word 
as the previous read transfer, no new flash read is done and the read data is given without 
wait cycles.

When an AHB data-port read transfer requires data from a different flash word to that 
involved in the previous read transfer, a new flash read is done and wait states are given 
until the new read data is available.

With dual buffering a secondary buffer line is used, the output of the flash being 
considered as the primary buffer. On a primary buffer hit data can be copied to the 
secondary buffer line, which allows the flash to start a speculative read of the next flash 
word.